Multiple input/gain stage Gilbert cell mixers
View Patent ↗Multiple input and/or gain stage Gilbert cell mixer designs are disclosed. The designs allow one input to be turned on at a time, and are suitable, for example, for use in receiver and transmitter applications. In addition, the designs allow for the inputs of the multi-input Gilbert cell mixer to be connected together, thereby allowing for switching of gain states within the Gilbert cell mixer. The mixer design may include, for example, a Gilbert cell mixer stage, and a plurality of input/gain stages. Each input/gain stage has its output connected to the input of the mixer stage, and is configured for receiving an input signal and applying a gain factor to that input signal to provide a signal for mixing with the LO. Each input/gain stage is configured with stage select circuitry for enabling or disabling that stage, so that only one input/gain stage is active at a time.
1. A mixer circuit device comprising:
a Gilbert cell mixer stage for multiplying a first signal received at an input by a second signal to provide an output signal; and
a plurality of input/gain stages, each input/gain stage having its output connected to the input of the mixer stage and for receiving a differential input signal and applying a gain factor to that differential input signal to provide the first signal, wherein each input/gain stage is configured with stage select circuitry for enabling or disabling that stage, and wherein each of the input/gain stages includes a differential transistor pair for receiving said differential input signal and that is biased using the corresponding stage select circuitry, and the differential transistor pair of a first of the input/gain stages is implemented with a first transistor technology for providing the corresponding gain factor and the differential transistor pair of a second of the input/gain stages is implemented with a second transistor technology for providing the corresponding gain factor, the second transistor technology being different from the first transistor technology and wherein one of the first or second transistor technologies allows the mixer circuit to have higher output intercept points than the other of the first or second transistor technologies.
2. The device of claim 1 wherein each of the input/gain stages is configured with emitter degeneration and only one of the input/gain stages is enabled at a time.
3. The device of claim 1 wherein multi-gain stage functionality enabled by the device incurs a 10% or lower increase in noise figure degradation, relative to noise figure of a comparable single gain stage configuration.
4. The device of claim 1 wherein the first transistor technology is heterojunction bipolar transistor (HBT) technology, and the second transistor technology is complementary metal oxide semiconductor (CMOS) field effect transistor (FET) technology.
5. The device of claim 1 wherein each stage select circuitry includes a current source, and each of the current sources is implemented as a current mirror with emitter degeneration.
6. The device of claim 1 wherein each input/gain stage receives a corresponding one of multiple differential input signals.
7. The device of claim 1 wherein inputs of the input/gain stages are tied together so that each input/gain stage receives a common differential input signal.
8. The device of claim 1 wherein at least one of the input/gain stages has a different gain than others of the input/gain stages.
9. The device of claim 1 wherein the device is included in a system-on-chip configuration.
10. An integrated circuit comprising:
a Gilbert cell mixer stage for multiplying a first signal received at an input by a second signal to provide an output signal; and
a plurality of input/gain stages, each input/gain stage having its output connected to the input of the mixer stage and for receiving a differential input signal and applying a gain factor to that differential input signal to provide the first signal, wherein each input/gain stage is configured with stage select circuitry for enabling or disabling that stage;
wherein the plurality of input/gain stages is implemented with at least two different transistor technologies, and each of the input/gain stages further includes a differential transistor pair for receiving said differential input signal and that is implemented with a corresponding one of the at least two different transistor technologies and biased using the corresponding stage select circuitry, and wherein one of the at least two different transistor technologies allows the integrated circuit to have higher output intercept points than the others of the at least two different transistor technologies.
11. The integrated circuit of claim 10 wherein at least one stage select circuitry is configured with a current source implemented as a current mirror with emitter degeneration.
12. The integrated circuit of claim 10 wherein the at least two different transistor technologies include bipolar junction transistor (BJT) technology, heterojunction bipolar transistor (HBT) technology, and/or complementary metal oxide semiconductor (CMOS) field effect transistor (FET) technology.
13. The integrated circuit of claim 10 wherein each input/gain stage receives a corresponding one of multiple differential input signals.
14. The integrated circuit of claim 10 wherein inputs of the input/gain stages are tied together so that each input/gain stage receives a common differential input signal.
15. The integrated circuit of claim 10 wherein at least one of the input/gain stages has a different gain than others of the input/gain stages.
16. A system comprising:
a circuit for at least one of transmitting or receiving communication signals, the circuit including a mixer device, the mixer device comprising:
a Gilbert cell mixer stage for multiplying a first signal received at an input by a second signal to provide an output signal; and
a plurality of input/gain stages, each input/gain stage having its output connected to the input of the mixer stage and for receiving a differential input signal and applying a gain factor to that differential input signal to provide the first signal, wherein each input/gain stage is configured with stage select circuitry for enabling or disabling that stage;
wherein the plurality of input/gain stages is implemented with at least two different transistor technologies, and each of the input/gain stages further includes a differential transistor pair for receiving said differential input signal and that is implemented with a corresponding one of the at least two different transistor technologies and biased using the corresponding stage select circuitry, and wherein one of the at least two different transistor technologies allows the circuit to have higher output intercept points than the others of the at least two different transistor technologies, and each stage select circuitry includes a current source.
17. The system of claim 16 wherein at least one of the current sources is implemented as a current mirror with emitter degeneration.
18. The system of claim 16 wherein each input/gain stage receives a corresponding one of multiple differential input signals.
19. The system of claim 16 wherein inputs of the input/gain stages are tied together so that each input/gain stage receives a common differential input signal.
20. The system of claim 16 wherein at least one of the input/gain stages has a different gain than others of the input/gain stages.
21. A mixer circuit device comprising:
a Gilbert cell mixer stage for multiplying a first signal received at an input by a second signal to provide an output signal; and
a plurality of input/gain stages, each input/gain stage having its output connected to the input of the mixer stage and for receiving a corresponding one of multiple differential input signals and applying a gain factor to that differential input signal to provide the first signal, wherein the plurality of input/gain stages is implemented with at least two different transistor technologies, and each input/gain stage is further configured with stage select circuitry for enabling or disabling that stage and a differential transistor pair for receiving its corresponding differential input signal and that is implemented with a corresponding one of the at least two different transistor technologies, and wherein one of the at least two different transistor technologies allows the mixer circuit to have higher output intercept points than the others of the at least two different transistor technologies.
22. The integrated circuit of claim 21 wherein at least one stage select circuitry is configured with a current source configured with emitter degeneration, and at least one of the input/gain stages has a different gain than others of the input/gain stages.