Architecture and method for memory programming
Methods of programming a memory, memory devices, and systems are disclosed, for example. In one such method, each data line of a memory to be programmed is biased differently depending upon whether one or more of the data lines adjacent the data line are inhibited. In one such system, a connection circuit provides data corresponding to the inhibit status of a target data line to page buffers associated with data lines adjacent to the target data line.
1. A method of programming a memory, comprising:
determining an inhibit status of data lines adjacent to a data line to be programmed; and
adjusting a data line voltage of the data line to be programmed when at least one of the adjacent data lines is inhibited.
2. The method of claim 1 , wherein the adjusted data line voltage is between a program voltage and an inhibit voltage.
3. The method of claim 2 , wherein the adjusted data line voltage is higher when both adjacent data lines are inhibited.
4. The method of claim 2 , wherein the adjusted data line voltage is approximately 0.8 volts when a single adjacent data line is inhibited.
5. The method of claim 2 , wherein the adjusted data line voltage is approximately 1.3 volts when both adjacent data lines are inhibited.
6. The method of claim 1 , wherein adjusting a data line voltage comprises latching a logic 1 signal into either a first latch or a second latch depending upon the inhibit status of the data lines adjacent to the data line to be programmed, wherein a logic 1 signal is latched into the first latch when one of the data lines adjacent to the data line to be programmed is inhibited, and wherein a logic 1 signal is latched into the second latch when both of the data lines adjacent to the data line to be programmed are inhibited.
7. The method of claim 6 , wherein adjusting a data line voltage further comprises applying a voltage of approximately 0.8 volts when a logic 1 signal is latched into the first latch, and applying a voltage of approximately 1.3 volts when a logic 1 signal is latched into the second latch.
8. The method of claim 1 , wherein determining an inhibit status comprises:
providing between a plurality of target page buffers each associated with one target data line and a plurality of adjacent page buffers each also associated with one data line a status of the one data line associated with each target page buffer; and
storing in a pair of latches for each adjacent page buffer whether zero, one, or two adjacent data lines associated with the adjacent page buffers are inhibited.
9. A method of programming a memory, comprising:
determining an inhibit status of data lines adjacent to a data line to be programmed; and
adjusting a data line voltage of the data line to be programmed when at least one of the adjacent data lines is inhibited;
wherein determining an inhibit status comprises:
providing between a plurality of target page buffers each associated with one target data line and a plurality of adjacent page buffers each also associated with one data line a status of the one data line associated with each target page buffer; and
storing in a pair of latches for each adjacent page buffer whether zero, one, or two adjacent data lines associated with the adjacent page buffers are inhibited; and
wherein adjusting a data line voltage further comprises:
applying a first intermediate voltage to each target data line having one adjacent data line inhibited, and applying a second intermediate voltage to each target data line having two adjacent data lines inhibited.
10. The method of claim 8 , wherein the first intermediate voltage is lower than the second intermediate voltage.
11. A method of programming a memory, comprising:
determining for a data line to be programmed a number of adjacent data lines that are inhibited; and
adjusting a data line voltage of the data line to be programmed when the number of adjacent data lines that are inhibited is greater than zero.
12. The method of claim 11 , wherein adjusting comprises raising the data line voltage when the number of adjacent data lines that are inhibited is greater than zero.
13. The method of claim 12 , wherein adjusting further comprises raising the data line voltage by a larger amount when a larger number of adjacent data lines are inhibited.
14. The method of claim 11 , wherein adjusting the data line voltage comprises adjusting to a level between a program voltage and an inhibit voltage.
15. The method of claim 11 , wherein adjusting a data line voltage further comprises:
applying a first bias voltage to the data line to be programmed when one of the data lines adjacent the data line to be programmed is inhibited; and
applying a second bias voltage higher than the first bias voltage to the data line to be programmed when both of the data lines adjacent the data line to be programmed are inhibited.
16. The method of claim 11 , wherein determining further comprises:
latching data indicative of the number of adjacent data lines that are inhibited.
17. The method of claim 16 , wherein latching further comprises:
latching into one of a first and a second latch a signal indicative of the number of adjacent data lines that are inhibited, wherein when one adjacent data line is inhibited, a logic 1 is latched into the first latch, and wherein when two adjacent data lines are inhibited, a logic 1 is latched into the second latch.
18. A method of programming a memory, comprising:
determining for a data line to be programmed a number of adjacent data lines that are inhibited; and
adjusting a data line voltage of the data line to be programmed when the number of adjacent data lines that are inhibited is greater than zero
wherein determining a number of adjacent data lines that are inhibited comprises:
determining for each of a plurality of data lines of the memory its status;
storing the inhibit status of each of the plurality of data lines in the memory in a respective page buffer for that data line; and
communicating to the page buffer for each data line that is to be programmed the stored inhibit status of its adjacent data lines.
19. The method of claim 18 , and further comprising:
storing in a pair of latches for each page buffer whether zero, one, or two adjacent data lines are inhibited.
20. The method of claim 19 , wherein storing comprises latching into one of a first and a second latch a signal indicative of the number of adjacent data lines that are inhibited, wherein when one adjacent data line is inhibited, a logic 1 is latched into the first latch, and wherein when two adjacent data lines are inhibited, a logic 1 is latched into the second latch.