Transistor and method for fabricating the same
A method for fabricating a semiconductor device to enlarge a channel region is provided. The channel region is enlarged due to having pillar shaped sidewalls of a transistor. The transistor includes a fin active region vertically protruding on a substrate, an isolation layer enclosing a lower portion of the fin active region, and a gate electrode crossing the fin active region and covering a portion of the fin active region. An isolation layer is formed enclosing a lower portion of the fin active region and the isolation layer under the spacers is partially removed to expose a portion of the sidewalls of the fin active region. Subsequently, dry etching is performed to form the sidewalls having a pillar/neck.
1. A method for fabricating a transistor, the method comprising:
forming a trench by partially etching a substrate to form a fin active region that protrudes vertically from the substrate;
forming an isolation structure around a lower portion of the fin active region while exposing an upper portion of the fin active region;
forming spacers on the upper portion of the fin active region;
partially removing the isolation structure under the spacers to expose a portion of sidewalls of the fin active region; and
etching the exposed portion of the sidewalls of the fin active region so that the fin active region defines an upper region, a middle region, and a lower region, the middle region being thinner than the upper region, wherein the etching process is a dry etch process using hydrogen chloride (HCl) as an etchant and exposes an uppermost surface of the lower region, side surfaces of the middle region, and a bottom surface of the upper region, a height of the uppermost surface of the lower region being equal to a height of a resulting upper surface of the isolation structure after said act of etching the exposed portion of the sidewalls of the fin active region.
2. The method of claim 1 , wherein further comprising, forming a pad nitride layer over the fin active region.
3. The method of claim 1 , wherein forming the isolation structure comprises filling in the trench with an isolation layer and etching the isolation layer to have a given thickness.
4. The method of claim 3 , wherein the thickness of the etched isolation layer defines the lower portion of the fin active region.
5. The method of claim 3 , wherein etching the isolation layer to have the given thickness is performed for a portion of the isolation layer corresponding to a target region where a gate electrode is formed.
6. The method of claim 1 , wherein the spacers include a nitride layer.
7. The method of claim 1 , wherein a wet etching process is performed to partially remove the isolation structure.
8. The method of claim 1 , wherein the etching process is performed by using an enchant that etches the substrate faster than the spacer or the isolation structure.
9. The method of claim 8 , wherein the etching process is performed at a temperature ranging from approximately 700° C. to approximately 1,000° C.
10. The method of claim 8 , wherein the etching process is performed at a pressure ranging from approximately 2 Torr to approximately 200 Torr.
11. The method of claim 8 , wherein the etching process is performed for approximately 0.5 minute to approximately 60 minutes.
12. The method of claim 1 , wherein the etching process uses a mixture of HCl and hydrogen (H 2 ) as an etchant.
13. The method of claim 12 , wherein the HCl has a flow ratio ranging from approximately 0.1 slm to approximately 1 slm and the H 2 has a flow ratio ranging from approximately 10 slm to approximately 50 slm.
14. The method of claim 1 , further comprising, prior to performing the etching, performing a thermal treatment on the fin active region.
15. The method of claim 14 , wherein the thermal treatment is performed at a temperature ranging from approximately 800° C. to approximately 1,000° C. and in an hydrogen (H 2 ) atmosphere.
16. The method of claim 1 , further comprising, after performing the vapor etching process:
forming a gate insulation layer on a surface of the fin active region and forming a gate electrode crossing the fin active region and covering a portion of the fin active region.