Display device and electronic equipment
The present invention provides a display device including a pixel array section, the pixel array section having pixels arranged in a matrix form, each of the pixels including: an electro-optical element; a write transistor; a holding capacitance; a drive transistor; and a switching transistor; a write scan line disposed for each of pixel rows of the pixel array section and adapted to convey a write signal to be applied to the gate electrode of the write transistor; and a correction scan line, wherein the wiring structure of the write scan line does not intersect with the wiring pattern connected to the gate electrode of the drive transistor.
1. A display device comprising:
a pixel array section, the pixel array section having pixels arranged in a matrix form, each of the pixels including
an electro-optical element,
a write transistor configured to write a video signal,
a holding capacitance configured to hold the video signal written by the write transistor,
a drive transistor configured to drive the electro-optical element based on the video signal held by the holding capacitance, and
a switching transistor configured to selectively write a reference potential serving as a reference for the video signal to a gate electrode of the drive transistor;
a write scan line disposed for each of the pixel rows of the pixel array section and configured to convey a write signal to be applied to a gate electrode of the write transistor; and
a correction scan line disposed for each of the pixel rows of the pixel array section and configured to convey a correction scan signal to be applied to a gate electrode of the switching transistor, the correction scan line being disposed outward of the pixel array section, and
wherein a wiring structure of the write scan line does not intersect with a wiring pattern connected to the gate electrode of the drive transistor and the write scan line is disposed further outward of the correction scan line and is electrically connected to the gate electrode of the write transistor via another wiring pattern formed on a wiring layer different from a wiring layer of the write scan line.
2. The display device of claim 1 , wherein
the pixel further includes a light emission control transistor configured to control the light emission and non-light emission of the electro-optical element;
the light emission control scan line configured to convey a light emission drive signal to be applied to a gate electrode of the light emission control transistor is disposed on the opposite side of the write scan line with the region where the components of the pixel are disposed therebetween, and
the light emission control scan line is electrically connected to the gate electrode of the light emission control transistor via a wiring pattern formed on a wiring layer different from a wiring layer of the light emission control scan line.
3. An electronic equipment comprising
a display device, including
a pixel array section, the pixel array section having pixels arranged in a matrix form, each of the pixels including,
an electro-optical element,
a write transistor configured to write a video signal,
a holding capacitance configured to hold the video signal written by the write transistor,
a drive transistor configured to drive the electro-optical element based on the video signal held by the holding capacitance, and
a switching transistor configured to selectively write a reference potential serving as a reference for the video signal to a gate electrode of the drive transistor;
a write scan line disposed for each of the pixel rows of the pixel array section and configured to convey a write signal to be applied to a gate electrode of the write transistor; and
a correction scan line disposed for each of the pixel rows of the pixel array section and configured to convey a correction scan signal to be applied to a gate electrode of the switching transistor, the correction scan line being disposed outward of the pixel array section, and wherein
a wiring structure of the write scan line does not intersect with a wiring pattern connected to the gate electrode of the drive transistor and the write scan line is disposed further outward of the correction scan line and is electrically connected to the gate electrode of the write transistor via another wiring pattern formed on a wiring layer different from a wiring layer of the write scan line.