Two dimensional memory access controller

1. A data processing system including a display, the display having a display surface, the system comprising:

logic to derive a two dimensional pixel location on a display screen from address signals of a graphics processing unit (GPU);

logic to compare the derived two dimensional pixel location to a two dimensional range of authorized pixel locations corresponding to a subset of a display surface;

logic to modify the address signals of a graphics processing unit (GPU) if the address signals do not fall within the two-dimensional range of authorized pixel locations corresponding to the subset of the display surface, and to propagate the address signals unmodified to a display memory otherwise.

2. The data processing system of claim 1 , wherein the logic to modify the address signals of a graphics processing unit further comprises:

logic to re-direct a data value by modifying a value of the address signals.

3. The data processing system of claim 1 , wherein the logic to modify the address signals of a graphics processing unit further comprises:

logic disposed between the GPU and the display memory.

4. The data processing system of claim 1 , further comprising:

the two dimensional range of authorized pixel locations identified horizontal range and a vertical range.

5. The data processing system of claim 4 , wherein the two dimensional range of authorized pixel locations identified by a horizontal range and a vertical range further comprises:

the horizontal range comprising a plurality of values each corresponding to a column of the display, and the vertical range comprising a plurality of values each corresponding to a row of the display.

6. The data processing system of claim 4 , further comprising:

logic to set the horizontal range and the vertical range in increments.

7. The data processing system of claim 1 , further comprising:

logic to redirect addresses within a fixed refresh buffer address range to a current display buffer address range.

8. The data processing system of claim 1 , further comprising:

logic to redirect unauthorized READs to a fixed address range.

9. The data processing system of claim 1 , further comprising:

logic to redirect unauthorized WRITEs to a fixed address range.

10. A data processing system including a display, the display having a display surface, the system comprising:

logic to intercept addresses between a graphics processing unit (GPU) and a display memory, and to modify values of unauthorized addresses but not modify values of authorized addresses;

wherein it is determined if the addresses are authorized addresses by deriving a two dimensional pixel location on a display screen from the addresses, and comparing the derived two dimensional pixel location to a two dimensional range of authorized pixel locations corresponding to a subset of the display surface.

11. The data processing system of claim 10 , further comprising:

logic to pipeline the addresses and control signals.

12. The data processing system of claim 10 , further comprising:

logic to pass data directly between the GPU and the display memory.

13. The data processing system of claim 10 , further comprising:

logic to re-direct READ operations in a fixed range corresponding to a refresh buffer to one of multiple selectable frame buffers.