Liquid crystal display panel of line on glass type and method of fabricating the same
A LOG-type liquid crystal display panel and a fabricating method thereof that reduces a line resistance of a LOG-type signal line group within the confined area. In the panel, a picture display part has a plurality of liquid crystal cells, each of which is arranged at each crossing area between gate lines and data lines. Line on glass type signal lines are provided at an outer area of the picture display part by a line on glass system to apply driving signals required for driver integrated circuits for driving the gate lines and the data lines and to connect the driver integrated circuits to each other. The line on glass type signal lines are separately provided at different metal layers having an insulating film therebetween.
1. A line on glass type liquid crystal display panel, comprising:
a picture display part having a plurality of liquid crystal cells, each of which is arranged at each crossing area between gate lines and data lines;
data tape carrier packages (“TCPs”) connected with one side of the liquid crystal display panel for driving the data lines, wherein the data TCPs include data driver integrated circuits (“ICs”) and are electrically connected with a data printed circuit board (“PCB”) for driving the data lines, respectively,
gate TCPs connected with one side of the liquid crystal display panel for driving the gate lines, wherein the gate TCPs include gate driver ICs for driving the gate lines, respectively, and
line on glass type (“LOG”) signal lines being provided at an outer area of the picture display part, wherein the LOG signal lines are located between a first data TCP and a first gate TCP, physically separated from the gate lines, and apply gate driving signals received from a timing controller and a power supply through the data PCB and the first data TCP to the gate driver ICs, wherein the gate driving signals include at least a gate low voltage, a gate high voltage, a ground voltage, a supply voltage, a gate start pulse and gate shift clock signals;
wherein the LOG signal lines includes first LOG signal line, applying the gate low voltage, and second LOG signal lines, applying different gate driving signals, that are separately provided at different metal layers having an insulating film therebetween, and a width of the first LOG signal line applying the gate low voltage is greater than each width of the second LOG signal lines applying the different gate signals, so that the first LOG signal line applying the gate low voltage prevents a cross-line phenomenon between blocks respectively connected to the gate driver ICs,
wherein the first LOG signal line applying the gate low voltage overlaps at least three second LOG signal lines applying the different gate driving signals over/below the second LOG signal lines, the first LOG signal line is formed along the at least three second LOG signal lines at an entire area between the at least three second LOG signal lines, the first LOG signal line is longitudinally parallel with the at least three second LOG signal lines and the width of the first LOG signal line is greater than a sum of width of the at least three second LOG signal lines.
2. The line on glass type liquid crystal display panel according to claim 1 , wherein the LOG signal lines are provided separately at a gate metal layer and a source/drain metal layer that have the gate insulating film therebetween.
3. The line on glass type liquid crystal display panel according to claim 1 , wherein the second LOG signal lines further comprises a LOG signal line supplying a common voltage required for a common electrode included in the picture display part.
4. The line on glass type liquid crystal display panel according to claim 3 , wherein the first LOG signal line is formed from a gate metal layer and the second LOG signal lines are formed from a source/drain metal layer.
5. The line on glass type liquid crystal display panel according to claim 3 , wherein the first LOG signal line is formed from a source/drain metal layer and the second LOG signal lines are formed from a gate metal layer.