Magnetoresistive random access memory (MRAM) with integrated magnetic film enhanced circuit elements
A Magnetoresistive Random Access Memory (MRAM) integrated circuit includes a substrate, a magnetic tunnel junction region, a magnetic circuit element, and an integrated magnetic material. The magnetic tunnel junction region is disposed on the substrate, and includes a first magnetic layer and a second magnetic layer separated by a tunnel barrier insulating layer. The magnetic circuit element region is disposed on the substrate, and includes a plurality of interconnected metal portions. The integrated magnetic material is disposed on the substrate adjacent to the plurality of interconnected metal portions.
1. A Magnetoresistive Random Access Memory integrated circuit, the integrated circuit comprising:
a substrate;
a magnetic tunnel junction region disposed on the substrate, the magnetic tunnel junction region comprising a first magnetic layer and a second magnetic layer separated by a tunnel barrier insulating layer;
a magnetic circuit element region disposed on the substrate, the magnetic circuit element region comprising a plurality of interconnected metal portions; and
a first integrated magnetic material disposed on the substrate adjacent to the plurality of interconnected metal portions.
2. The integrated circuit of claim 1 , wherein the first integrated magnetic material is disposed on the substrate in the same plane as at least one of the first and second magnetic layers of the magnetic tunnel junction.
3. The integrated circuit of claim 1 , wherein the first integrated magnetic material is disposed on the substrate in a different plane from the first and second magnetic layers of the magnetic tunnel junction.
4. The integrated circuit of claim 1 , wherein the first integrated magnetic material is a magnetic film comprising a first magnetic layer corresponding to and coplanar with the first magnetic layer of the magnetic tunnel junction, a second magnetic layer corresponding to and coplanar with the second magnetic layer of the magnetic tunnel junction, and an insulating layer corresponding to and coplanar with the tunnel barrier insulating layer of the magnetic tunnel junction.
5. The integrated circuit of claim 4 , wherein the magnetic film further comprises a cap insulating layer disposed on the second magnetic layer of the magnetic film.
6. The integrated circuit of claim 1 , further comprising a second integrated magnetic material disposed on the substrate adjacent to the plurality of interconnected metal portions and isolated from the first integrated magnetic material.
7. The integrated circuit of claim 1 , wherein the first integrated magnetic material is formed from a plurality of strips of magnetic material.
8. The integrated circuit of claim 7 , wherein the strips of magnetic material are arranged in a striped, checkered, partially staggered, or fully staggered pattern.
9. The integrated circuit of claim 1 , wherein the first integrated magnetic material and at least one of the first and second magnetic layers of the magnetic tunnel junction have a common magnetic moment from a shared magnetic anneal.
10. The integrated circuit of claim 1 , wherein the magnetic circuit element is an inductor or a transformer.
11. The integrated circuit of claim 1 integrated in at least one semiconductor die.
12. The integrated circuit of claim 1 further comprising a device, selected from the group consisting of a set top box, music player, video player, entertainment unit, navigation device, communications device, personal digital assistant (PDA), fixed location data unit, and a computer, into which the integrated circuit is integrated.
13. A method of forming a Magnetoresistive Random Access Memory integrated circuit, the method comprising:
providing a substrate;
depositing and patterning a first magnetic layer, a tunnel barrier insulating layer, and a second magnetic layer to form a magnetic tunnel junction region on the substrate;
depositing and patterning a plurality of interconnected metal portions to form a magnetic circuit element region on the substrate; and
depositing and patterning a first integrated magnetic material on the substrate adjacent to the plurality of interconnected metal portions.
14. The method of claim 13 , wherein the first integrated magnetic material and at least one of the first and second magnetic layers of the magnetic tunnel junction are deposited and patterned together on the substrate and in the same plane.
15. The method of claim 13 , wherein the first integrated magnetic material and the first and second magnetic layers of the magnetic tunnel junction are deposited and patterned separately on the substrate and in different planes.
16. The method of claim 13 , wherein depositing and patterning the first integrated magnetic material comprises forming a magnetic film by depositing and patterning a first magnetic layer corresponding to and coplanar with the first magnetic layer of the magnetic tunnel junction, a second magnetic layer corresponding to and coplanar with the second magnetic layer of the magnetic tunnel junction, and an insulating layer corresponding to and coplanar with the tunnel barrier insulating layer of the magnetic tunnel junction.
17. The method of claim 16 , wherein forming the magnetic film further comprises providing a cap insulating layer on the second magnetic layer of the magnetic film.
18. The method of claim 13 , further comprising depositing and patterning a second integrated magnetic material on the substrate adjacent to the plurality of interconnected metal portions and isolated from the first integrated magnetic material.
19. The method of claim 13 , wherein depositing and patterning the first integrated magnetic material comprises forming a plurality of strips of magnetic material.
20. The method of claim 19 , wherein depositing and patterning the first integrated magnetic material further comprises arranging the strips of magnetic material in a striped, checkered, partially staggered, or fully staggered pattern.
21. The method of claim 13 , further comprising applying a shared magnetic anneal to the first integrated magnetic material and at least one of the first and second magnetic layers of the magnetic tunnel junction to provide a common magnetic moment.
22. The method of claim 13 , wherein the magnetic circuit element is an inductor or a transformer.
23. A Magnetoresistive Random Access Memory integrated circuit, the integrated circuit comprising:
a substrate;
a magnetic tunnel junction region disposed on the substrate, the magnetic tunnel junction region comprising a first magnetic layer and a second magnetic layer separated by a tunnel barrier insulating layer;
a magnetic circuit element region disposed on the substrate, the magnetic circuit element region comprising a plurality of interconnected metal portions; and
first magnetic means for concentrating a magnetic field, the first magnetic means disposed on the substrate adjacent to the plurality of interconnected metal portions.
24. The integrated circuit of claim 23 , wherein the first magnetic means is disposed on the substrate in the same plane as at least one of the first and second magnetic layers of the magnetic tunnel junction.
25. The integrated circuit of claim 23 , further comprising a second magnetic means for concentrating a magnetic field, the second magnetic means disposed on the substrate adjacent to the plurality of interconnected metal portions and isolated from the first magnetic means.
26. The integrated circuit of claim 23 , wherein the first means is divided into a plurality of strips isolated from each other.
27. The integrated circuit of claim 23 , wherein the first magnetic means and at least one of the first and second magnetic layers of the magnetic tunnel junction have a common magnetic moment from a shared magnetic anneal.
28. A method of forming a Magnetoresistive Random Access Memory integrated circuit, the method comprising:
step for providing a substrate;
step for depositing and patterning a first magnetic layer, a tunnel barrier insulating layer, and a second magnetic layer to form a magnetic tunnel junction region on the substrate;
step for depositing and patterning a plurality of interconnected metal portions to form a magnetic circuit element region on the substrate; and
step for depositing and patterning a first integrated magnetic material on the substrate adjacent to the plurality of interconnected metal portions.
29. The method of claim 28 , wherein the step for depositing and patterning the first integrated magnetic material comprises step for forming a magnetic film by depositing and patterning a first magnetic layer corresponding to and coplanar with the first magnetic layer of the magnetic tunnel junction, a second magnetic layer corresponding to and coplanar with the second magnetic layer of the magnetic tunnel junction, and an insulating layer corresponding to and coplanar with the tunnel barrier insulating layer of the magnetic tunnel junction.
30. The method of claim 28 , further comprising step for depositing and patterning a second integrated magnetic material on the substrate adjacent to the plurality of interconnected metal portions and isolated from the first integrated magnetic material.
31. The method of claim 28 , wherein the step for depositing and patterning the first integrated magnetic material comprises step forming a plurality of strips of magnetic material.
32. The method of claim 28 , further comprising step for applying a shared magnetic anneal to the first integrated magnetic material and at least one of the first and second magnetic layers of the magnetic tunnel junction to provide a common magnetic moment.