IP Library › Granted Patent US 8,253,398
Granted Patent B2
US 8,253,398 · App. 12/500,015 · Granted Aug 28, 2012

Semiconductor device

Assignee: Kabushiki Kaisha Toshiba
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Quick Facts
Patent No.
US 8,253,398
App. No.
12/500,015
Granted
Aug 28, 2012
Kind
B2
Abstract

A semiconductor device includes: a high-side switching element having a first switching element connected between an input voltage line and an inductive load; and a low-side switching element having a second switching element and a third switching element that are connected in parallel between the inductive load and a reference voltage line. A surge current is discharged through the third switching element to the reference voltage line when a surge is applied to a terminal connected to the inductive load in the low-side switching element.

Claims (17)

1. A semiconductor device comprising:

a high-side switching element having a first switching element connected between an input voltage line and an inductive load; and

a low-side switching element having a second switching element and a third switching element that are connected in parallel between the inductive load and a reference voltage line,

a surge current being discharged through the third switching element to the reference voltage line when a surge is applied to a terminal connected to the inductive load in the low-side switching element, wherein

the low-side switching element comprises, a semiconductor layer of a first conductivity type, a source layer of a second conductivity type provided on a portion of the semiconductor layer, a drain layer of the second conductivity type provided so as to be separate from the source layer on a portion of the semiconductor layer, a drift layer of the second conductivity type provided to contact the drain layer between the source layer and the drain layer and having lower impurity concentration than that of the drain layer, a first main electrode connected to the drain layer, a second main electrode connected to the source layer, and a gate electrode provided through an insulating film on a surface of the semiconductor layer between the source layer and the drift layer, and L1>L2 being satisfied, where L1 is a length of the drift layer in the second switching element and L2 is a length of the drift layer in the third switching element, and

the third switching element has lower breakdown voltage than that of the second switching element.

2. The device according to claim 1 , wherein the third switching element comprises:

a main current path connecting the first main electrode and the second main electrode through the drain layer, the drift layer, a channel formed under the gate electrode, and the source layer; and

a surge current path provided between the first main electrode and the second main electrode in parallel to the main current path and activated by the surge to flow a surge current there through.

3. The device according to claim 2 , wherein the surge current flows through a thyristor.

4. The device according to claim 2 , wherein the surge current flows through a bipolar transistor.

5. The device according to claim 2 , wherein the surge current flows through a diode.

6. The device according to claim 1 , wherein the third switching element has lower current driving capability than that of the second switching element in a state of being applied a rated voltage, and a period, when the second switching element is set to be OFF and the third switching element is set to be ON, is provided during a period when a current flows from the inductive load through the low-side switching element to the reference voltage line.

7. The device according to claim 1 , further comprising a detection circuit to detect potential of a connecting point between the low-side switching element and the inductive load.

8. The device according to claim 7 , wherein when the potential of the connecting point is negative, the third switching element is turned OFF or turned ON-OFF at the same timing as the second switching element.

9. The device according to claim 7 , wherein during a period when the potential of the connecting point becomes positive, a period when the second switching element is set to be OFF and the third switching element is set to be ON is provided.

10. The device according to claim 1 , wherein the first switching element and the second switching element are not set to be ON simultaneously, and the first switching element and the third switching element are not set to be ON simultaneously.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jul 9, 2009
From: NAKAMURA, KAZUTOSHI; YASUHARA, NORIO
To: KABUSHIKI KAISHA TOSHIBA
Reel/Frame 022934/0235 →
Priority Claims (1)
JP 2008-184723 · Jul 16, 2008 · national
Continuity (1)
Related Publication 20100013451A1 · Jan 21, 2010