IP Library Granted Patent US 8,254,758
Granted Patent B2
US 8,254,758 · App. 12/219,246 · Granted Aug 28, 2012

Input-output circuit, recording apparatus and reproduction apparatus for digital video signal

Assignee: Hitachi Consumer Electronics Co., Ltd.
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Quick Facts
Patent No.
US 8,254,758
App. No.
12/219,246
Granted
Aug 28, 2012
Kind
B2
Abstract

A video signal input-output circuit and a recording-reproduction apparatus in which a digitally compressed video signal input in packet form can be recorded and reproduced efficiently and in stable fashion. In this apparatus, a clock reference is detected from a packet signal containing the clock reference and a digitally compressed video signal, a time stamp for a packet is generated using a clock signal in phase with the clock reference and added to the particular packet, and the packet signals with the time stamp added thereto are recorded closely to each other in a data storage element such as a magnetic recording medium. At playback, the packet interval is output by being restored to the original length on the basis of the time stamp added to the packet in store.

Claims (20)

1. A digital video signal recording method for recording a digitally compressed video signal on a recording medium having a recording area composed of a plurality of blocks, the digitally compressed video signal being an intermittent input signal in the form of fixed length packets, the method comprising the steps of:

inputting a digitally compressed video signal, the digitally compressed video signal being an intermittent input signal in the form of fixed length packets;

generating a reference clock of a predetermined frequency;

adding a time stamp to each packet based on the reference clock, the time stamp indicating an input timing of the packets; and

recording a number m of the packets in a number n of the blocks on the recording medium, n and m being predetermined integers (n<m).

2. An apparatus for recording a digitally compressed video signal on a recording medium having a recording area composed of a plurality of blocks, the digitally compressed video signal being an intermittent input signal in the form of fixed length packets, the apparatus comprising:

an input circuit which inputs a digitally compressed video signal, the digitally compressed video signal being an intermittent input signal in the form of fixed length packets,

a generation circuit which generates a reference clock of a predetermined frequency;

an adding circuit which adds a time stamp to the packets based on the reference clock, the time stamp indicating an input timing of the packets; and

a recording circuit which records a number m of the packets in a number n of the blocks on the recording medium, n and m being predetermined integers (n<m).

3. A method for reproducing a digitally compressed video signal recorded on a recording medium having a recording area composed of a plurality of blocks, the digitally compressed video signal being an intermittent input signal in the form of fixed length packets, the method comprising the steps of:

reproducing the packets recorded on the recording medium, the packets being recorded on the recording medium, the packets including a time stamp indicating an output timing of the packets, a number m of the packets being included in a number n of the blocks on the recording medium, n and m being predetermined integers (n<m);

generating a clock signal using a local oscillator;

adjusting the output timing of the reproduced packets based on the time stamp and the clock signal from the local oscillator so as to restore original time intervals of the intermittent input signal; and

outputting the adjusted packets.

4. An apparatus for reproducing a digitally compressed video signal recorded on a recording medium having a recording area composed of a plurality of blocks, the digitally compressed video signal being an intermittent input signal in the form of fixed length packets, the apparatus comprising:

a reproducing circuit which reproduces the packets recorded on the recording medium, the packets being recorded on the recording medium, the packets including a time stamp indicating an output timing of the packets, a number m of the packets being included in a number n of the blocks on the recording medium, n and m being predetermined integers (n<m);

a local oscillator which generates a clock signal;

an adjusting circuit which adjusts the output timing of the reproduced packets based on the time stamp and the clock signal from the local oscillator so as to restore original time intervals of the intermittent input signal; and

an output circuit which outputs the adjusted packets.

Assignments (3)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jan 25, 2018
From: HITACHI MAXELL, LTD.
To: MAXELL, LTD.
Reel/Frame 045142/0208 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Sep 8, 2014
From: HITACHI CONSUMER ELECTRONICS CO., LTD.; HITACHI CONSUMER ELECTRONICS CO, LTD.
To: HITACHI MAXELL, LTD.
Reel/Frame 033694/0745 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded May 27, 2010
From: HITACHI, LTD.
To: HITACHI CONSUMER ELECTRONICS CO., LTD.
Reel/Frame 024445/0332 →
Priority Claims (2)
JP 6-264874 · Oct 28, 1994 · national
JP 7-140294 · Jun 7, 1995 · national
Continuity (6)
Continuation 11936852 · Nov 8, 2007
Continuation 10367730 · Feb 19, 2003
Continuation 09455413 · Dec 6, 1999
Division 08972457 · Nov 18, 1997
Division 08547662 · Oct 24, 1995
Related Publication 20080292282A1 · Nov 27, 2008