Epitaxy profile engineering for FinFETs
View Patent ↗A method of forming an integrated circuit structure includes providing a wafer including a substrate and a semiconductor fin at a major surface of the substrate, and performing a deposition step to epitaxially grow an epitaxy layer on a top surface and sidewalls of the semiconductor fin, wherein the epitaxy layer includes a semiconductor material. An etch step is then performed to remove a portion of the epitaxy layer, with a remaining portion of the epitaxy layer remaining on the top surface and the sidewalls of the semiconductor fin.
1. A method of forming an integrated circuit structure, the method comprising:
providing a wafer comprising a substrate and a semiconductor fin at a major surface of the substrate;
performing a first deposition step to epitaxially grow a first epitaxy layer on a top surface and sidewalls of the semiconductor fin, wherein the first epitaxy layer comprises a semiconductor material; and
after the step of performing the first deposition step, performing a first etch step to remove a portion of the first epitaxy layer, with a remaining portion of the first epitaxy layer remaining on the top surface and the sidewalls of the semiconductor fin.
2. The method of claim 1 further comprising, before the step of performing the first deposition step, forming a gate dielectric and a gate electrode covering a portion of the semiconductor fin, wherein the epitaxy layer is grown from uncovered portions of the semiconductor fin.
3. The method of claim 1 , wherein the first deposition step and the first etch step are performed with no vacuum break therebetween.
4. The method of claim 1 further comprising performing a second deposition step to epitaxially grow a second epitaxy layer over and contacting the remaining portion of the first epitaxy layer.
5. The method of claim 4 further comprising, after the second deposition step, performing a second etch step to reduce a thickness of the second epitaxy layer.
6. The method of claim 5 , wherein after the second etch step, a remaining portion of the second epitaxy layer remains over the remaining portion of the epitaxy layer.
7. The method of claim 4 , wherein the first epitaxy layer and the second epitaxy layer are formed of a same semiconductor material.
8. The method of claim 1 , wherein the first deposition step is performed selectively with an etching gas introduced.
9. The method of claim 1 , wherein the first etch step is performed using HCl and GeH 4 as process gases.
10. A method of forming an integrated circuit structure, the method comprising:
providing a wafer comprising a substrate and a semiconductor fin at a major surface of the substrate;
forming a gate dielectric and a gate electrode covering a first portion of the semiconductor fin, with a second portion of the semiconductor fin uncovered by the gate dielectric and the gate electrode; and
performing a first deposition-etch cycle comprising:
performing a first deposition step to form a first epitaxy semiconductor layer on the second portion of the semiconductor fin; and
performing a first etch step to reduce a thickness of the first epitaxy semiconductor layer, wherein the first deposition step and the first etch step are in-situ performed with no vacuum break therebetween.
11. The method of claim 10 further comprising performing a second deposition-etch cycle comprising:
performing a second deposition step to form a second epitaxy semiconductor layer on the first epitaxy semiconductor layer; and
performing a second etch step to reduce a thickness of the second epitaxy semiconductor layer, wherein the second deposition step and the second etch step are in-situ performed with no vacuum break therebetween.
12. The method of claim 11 , wherein after the second etch step, a remaining portion of the second epitaxy semiconductor layer remains over the first epitaxy semiconductor layer.
13. The method of claim 11 , wherein the first epitaxy semiconductor layer and the second epitaxy semiconductor layer are formed of a same semiconductor material.
14. The method of claim 10 , wherein the first deposition step is performed selectively with an etching gas introduced.
15. The method of claim 10 , wherein the first etch step is performed using HCl and GeH 4 as process gases.
16. The method of claim 10 , wherein after the first etch step, a remaining portion of the first epitaxy semiconductor layer has an ellipse surface profile.
17. A method of forming an integrated circuit structure, the method comprising:
providing a wafer comprising:
a semiconductor substrate;
two shallow trench isolation (STI) regions in the semiconductor substrate; and
a semiconductor fin over, and horizontally between, the two STI regions;
forming a gate dielectric and a gate electrode covering a first portion of the semiconductor fin, with a second portion of the semiconductor fin uncovered by the gate dielectric and the gate electrode; and
performing a plurality of deposition-etch cycles, each comprising:
performing a deposition step to form an epitaxy layer over a top surface and sidewalls of the second portion of the semiconductor fin; and
performing an etch step to remove a portion of the epitaxy layer, with a remaining portion of the epitaxy layer remaining on the top surface and sidewalls of the second portion of the semiconductor fin.
18. The method of claim 17 , wherein the deposition step is selectively performed on the semiconductor fin, with substantially no epitaxy layer deposited on the two STI regions.
19. The method of claim 17 , wherein the deposition step is performed non-selectively on the semiconductor fin and the two STI regions.
20. The method of claim 17 , wherein the etch step is formed using process gases comprising HCl and GeH 4 .