Channel strain induced by strained metal in FET source or drain
A process for forming a FET (e.g., an n-FET or a p-FET), in which during formation a metal which makes up a source or drain of the transistor is stressed so that stress is induced in a semiconductor channel of the transistor.
1. A complementary process for forming field-effect transistors (FETs), comprising forming n-channel FETs having respective semiconductor channels in a tensile stress state and p-channel FETs having respective semiconductor channels in a compressive stress state, each of the respective n-channel transistors having a metal source/drain with a workfunction less than an affinity of a semiconductor that makes up the semiconductor channel of the respective n-channel transistor and each of the p-channel transistors having a respective metal source/drain with a workfunction greater than an ionization potential of a semiconductor that makes up the semiconductor channel of the respective p-channel transistor, wherein in each transistor instance, during the formation process, stress is induced in respective semiconductor channels of each respective n-channel or p-channel transistor by a strained capping metal which caps the metal source/drain of the respective n-channel or p-channel transistor and induces stress in each respective semiconductor channel.
2. The process of claim 1 , wherein stress in the metal source/drain of a respective transistor, at some point in the process, is at least 100 MPa.
3. The process of claim 1 , wherein for a position within the semiconductor channel of a respective transistor, a difference in stress relative to a case where all metals in the source/drain were unstressed, is at least 100 MPa, at the end of the process.
4. The process of claim 1 , wherein the stress in the metal source/drain of a respective transistor, at some point in the process, is at least 500 MPa.
5. The process of claim 1 , wherein for a position within a semiconductor channel of a respective transistor, a difference in stress relative to a case where all metals in the source or drain were unstressed, is at least 500 MPa, at the end of the process.
6. The process of claim 1 , wherein the metal source/drain of the respective transistors is separated from the respective semiconductor channels of the respective transistors by an additional layer.
7. The process of claim 1 wherein the metal source/drain of the respective transistors is, at some point in the process, strained, and contributes to the stress in the respective semiconductor channels of the respective transistors.