IP Library › Granted Patent US 8,263,484
Granted Patent B2
US 8,263,484 · App. 12/714,659 · Granted Sep 11, 2012

High resistivity silicon wafer and method for manufacturing the same

Assignee: Sumco Corporation
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Quick Facts
Patent No.
US 8,263,484
App. No.
12/714,659
Granted
Sep 11, 2012
Kind
B2
Abstract

This method for manufacturing a high resistivity silicon wafer includes pulling a single crystal such that the single crystal has a p-type dopant concentration at which a wafer surface resistivity becomes in a range of 0.1 to 10 k Ωcm, an oxygen concentration Oi of 5.0×10 17 to 20×10 17 atoms/cm 3 (ASTM F-121, 1979), and a nitrogen concentration of 1.0×10 13 to 10×10 13 atoms/cm 3 (ASTM F-121, 1979) by using a Czochralski method, processing the single crystal into wafers by slicing the single crystal, and subjecting the wafer to an oxygen out-diffusion heat treatment process in a non-oxidizing atmosphere.

Claims (40)

1. A method for manufacturing a high resistivity silicon wafer where a depth range of a p/n type conversion occurrence region from a wafer surface can be adjusted, the method comprising:

pulling a single crystal such that the single crystal has a p-type dopant concentration at which a wafer surface resistivity becomes in a range of 0.1 to 10 k Ωcm, an oxygen concentration Oi of 5.0×10 17 to 20×10 17 atoms/cm 3 (ASTM F-121, 1979), and a nitrogen concentration of 1.0×10 13 to 10×10 13 atoms/cm 3 (ASTM F-121, 1979) by using a Czochralski method;

processing the single crystal into wafers by slicing the single crystal; and

subjecting the wafer to an oxygen out-diffusion heat treatment process in a non-oxidizing atmosphere,

wherein a peak position of a resistivity serving as a boundary between a p-type region of a wafer surface side and a p/n conversion region of an inner side of a thickness direction is adjusted by the nitrogen concentration such that the peak position is set to a boundary depth in a range of 10 to 70 μm from the wafer surface.

2. The method for manufacturing a high resistivity silicon wafer according to claim 1 , wherein the method further comprises a heat treatment process for forming oxygen precipitate nuclei and/or a heat treatment process for forming oxygen precipitates, after the oxygen out-diffusion heat treatment process.

3. The method for manufacturing a high resistivity silicon wafer according to claim 2 , wherein the heat treatment process for forming oxygen precipitate nuclei is performed at a processing temperature of 600 to 800° C. for a processing time of 1 to 20 hours and a heat treatment process for forming oxygen precipitates is performed at a processing temperature of 1000 to 1100° C. for a processing time of 1 to 20 hours.

4. The method for manufacturing a high resistivity silicon wafer according to claim 1 , wherein the oxygen out-diffusion heat treatment process is performed at a processing temperature of 1100 to 1250° C. for a processing time of 1 to 5 hours in an atmosphere of argon gas, hydrogen gas or a mixed gas thereof.

5. The method for manufacturing a high resistivity silicon wafer according to claim 4 , wherein, the oxygen out-diffusion heat treatment process is conducted such that the p/n type conversion region due to occurrence of thermal donors is generated at a depth so as not to be brought into contact with either any device active region or any depletion layer region formed in contact therewith when a heat treatment in a device fabrication process is performed.

6. A method for manufacturing a high resistivity silicon wafer where a p/n type conversion region is not generated and which includes a p-type region with variation in a resistivity distribution set to a range of 0 to 30% across all portions in a wafer thickness direction with respect to a reference value set to a range of 0.1 to 10 k Ωcm, the method comprising:

pulling a single crystal such that the single crystal has a p-type dopant concentration at which a wafer surface resistivity becomes in a range of 0.1 to 10 k Ωcm, an oxygen concentration Oi of 5.0×10 17 to 20×10 17 atoms/cm 3 (ASTM F-121, 1979), and a nitrogen concentration of 1.0×10 13 to 10×10 13 atoms/cm 3 (ASTM F-121, 1979) by using a Czochralski method;

processing the single crystal into wafers by slicing the single crystal;

subjecting the wafer to an oxygen out-diffusion heat treatment process in a non-oxidizing atmosphere; and

subjecting the wafer to a heat treatment process for forming oxygen precipitate nuclei and/or a heat treatment process for forming oxygen precipitates.

7. A high resistivity silicon wafer which is a p-type wafer having a resistivity of 100 k Ωcm or more and having a denuded zone in a wafer surface,

wherein the high resistivity silicon wafer is manufactured by the method according to claim 1 and is doped with nitrogen, and

when a heat treatment in a device fabrication process is performed, a p/n type conversion region due to occurrence of thermal donors is generated at a depth so as not to be brought into contact with either any device active region or any depletion layer region formed in contact therewith, or the p/n type conversion region is not generated.

8. The high resistivity silicon wafer according to claim 7 , wherein the p/n type conversion region is generated in a depth range of 10 μm to 70 μm from a wafer surface.

9. The high resistivity silicon wafer according to claim 7 , wherein the p/n type conversion region includes oxygen precipitates.

10. The high resistivity silicon wafer according to claim 7 , wherein an oxygen concentration in the wafer is 1.0×10 13 to 10×10 13 atoms/cm 3 (ASTM F-121, 1979).

11. A method for manufacturing a high resistivity silicon wafer, which has a sufficient resistivity for reducing current loss occurring in a device region in which a voltage controller is to be formed in a radio transmission/reception circuit using a high frequency of 10 GHz to 100 GHz and having a power of about 10 mW to 100 mW, and where a depth range of a p/n type conversion occurrence region from a wafer surface can be adjusted, the method comprising:

pulling a single crystal such that the single crystal has a p-type dopant concentration at which a wafer surface resistivity becomes in a range of 0.1 to 10 k Ωcm, an oxygen concentration Oi of 5.0×10 17 to 20×10 17 atoms/cm 3 (ASTM F-121, 1979), and a nitrogen concentration of 1.0×10 13 to 10×10 13 atoms/cm 3 (ASTM F-121, 1979) by using a Czochralski method;

processing the single crystal into wafers by slicing the single crystal; and

subjecting the wafer to an oxygen out-diffusion heat treatment process in a non-oxidizing atmosphere,

wherein a peak position of a resistivity serving as a boundary between a p-type region of a wafer surface side and a p/n conversion region of an inner side of a thickness direction is adjusted by the nitrogen concentration such that the peak position is set to a boundary depth in a range of 10 to 70 μm from a wafer surface.

12. The method for manufacturing a high resistivity silicon wafer according to claim 11 , wherein the method further comprises a heat treatment process for forming oxygen precipitate nuclei and/or a heat treatment process for forming oxygen precipitates, after the oxygen out-diffusion heat treatment process.

13. The method for manufacturing a high resistivity silicon wafer according to claim 12 , wherein the heat treatment process for forming oxygen precipitate nuclei is performed at a processing temperature of 600 to 800° C. for a processing time of 1 to 20 hours and a heat treatment process for forming oxygen precipitates is performed at a processing temperature of 1000 to 1100° C. for a processing time of 1 to 20 hours.

14. The method for manufacturing a high resistivity silicon wafer according to claim 11 , wherein the oxygen out-diffusion heat treatment process is performed at a processing temperature of 1100 to 1250° C. for a processing time of 1 to 5 hours in an atmosphere of argon gas, hydrogen gas or a mixed gas thereof.

15. The method for manufacturing a high resistivity silicon wafer according to claim 14 , wherein, the oxygen out-diffusion heat treatment process is conducted such that the p/n type conversion region due to occurrence of thermal donors is generated at a depth so as not to be brought into contact with either any device active region or any depletion layer region formed in contact therewith when a heat treatment in a device fabrication process is performed.

16. A method for manufacturing a high resistivity silicon wafer, which has a sufficient resistivity for reducing current loss occurring in a device region in which a voltage controller is to be formed in a radio transmission/reception circuit using a high frequency of 10 GHz to 100 GHz and having a power of about 10 mW to 100 mW, where a p/n type conversion region is not generated, and which includes a p-type region with variation in a resistivity distribution set to a range of 0 to 30% across all portions in a wafer thickness direction with respect to a reference value set to a range of 0.1 to 10 k Ωcm, the method comprising:

pulling a single crystal such that the single crystal has a p-type dopant concentration at which a wafer surface resistivity becomes in a range of 0.1 to 10 k Ωcm, an oxygen concentration Oi of 5.0×10 17 to 20×10 17 atoms/cm 3 (ASTM F-121, 1979), and a nitrogen concentration of 1.0×10 13 to 10×10 13 atoms/cm 3 (ASTM F-121, 1979) by using a Czochralski method;

processing the single crystal into wafers by slicing the single crystal;

subjecting the wafer to an oxygen out-diffusion heat treatment process in a non-oxidizing atmosphere; and

subjecting the wafer to a heat treatment process for forming oxygen precipitate nuclei and/or a heat treatment process for forming oxygen precipitates.

17. A high resistivity silicon wafer, which is a p-type wafer to be subjected to a device process for allowing a voltage controller in a radio transmission/reception circuit using a high frequency of 10 GHz to 100 GHz and having a power of about 10 mW to 100 mW to be formed on a surface, which has a resistivity of 100 Ωcm or more, and where a denuded zone is formed in a wafer surface,

wherein the high resistivity silicon wafer is manufactured by the method according to claim 11 and is doped with nitrogen, and

when a heat treatment in a device fabrication process is performed, a p/n type conversion region due to occurrence of thermal donors is generated at a depth so as not to be brought into contact with either any device active region or any depletion layer region formed in contact therewith, or the p/n type conversion region is not generated.

18. The high resistivity silicon wafer according to claim 17 , wherein the p/n type conversion region is generated in a depth range of 10 μm to 70 μm from a wafer surface.

19. The high resistivity silicon wafer according to claim 17 , wherein the p/n type conversion region includes oxygen precipitates.

20. The high resistivity silicon wafer according to claim 17 , wherein an oxygen concentration in the wafer is 1.0×10 13 to 10×10 13 atoms/cm 3 (ASTM F-121, 1979).

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Mar 1, 2010
From: KURITA, KAZUNARI
To: SUMCO CORPORATION
Reel/Frame 024005/0648 →
Priority Claims (3)
JP 2009-049908 · Mar 3, 2009 · national
JP 2009-146996 · Jun 19, 2009 · national
JP 2009-200420 · Aug 31, 2009 · national
Continuity (1)
Related Publication 20100224968A1 · Sep 9, 2010