IP Library › Granted Patent US 8,264,021
Granted Patent B2
US 8,264,021 · App. 12/761,686 · Granted Sep 11, 2012

Finfets and methods for forming the same

Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
View Patent ↗
Loading inventors, assignments & file history…
Monitor This Case
Get email alerts when status or documents change.
Order Certified Copies
Most orders are placed with the USPTO same day — all within 24 business hours.
Order via The Patent Place →
Pre-filled with this patent's details
Quick Facts
Patent No.
US 8,264,021
App. No.
12/761,686
Granted
Sep 11, 2012
Kind
B2
Abstract

A Fin field effect transistor (FinFET) includes a fin-channel body over a substrate. A gate electrode is disposed over the fin-channel body. At least one source/drain (S/D) region is disposed adjacent to the fin-channel body. The at least one S/D region is substantially free from including any fin structure.

Claims (31)

1. A Fin field effect transistor (FinFET) comprising:

a fin-channel body over a substrate;

a gate electrode disposed over the fin-channel body; and

at least one source/drain (S/D) region disposed adjacent to the fin-channel body, the at least one S/D region being substantially free from including any fin structure, wherein

the substrate has a portion between a first isolation region and a second isolation region, the at least one S/D region includes an epitaxially-grown region, and the epitaxially-grown region is disposed over the portion of the substrate, and

the first isolation region has a corner where a surface of the first isolation region and an interface between the first isolation region and the portion of the substrate intersect, the portion of the substrate has a tip where a surface of the portion of the substrate and the interface between the first isolation region and the portion of the substrate intersect, and the corner is substantially adjacent to the tip.

2. The FinFET claim 1 , wherein the epitaxially-grown region and the portion of the substrate have an interface and a central region of the interface is below a surface of the first isolation region.

3. The FinFET of claim 2 , wherein a distance between the central region of the interface and the surface of the first isolation region is substantially equal to a height of the fin-channel body.

4. The FinFET of claim 2 , wherein the central region of the interface is substantially flat.

5. The FinFET claim 1 , wherein the epitaxially-grown region is configured for providing a stress to the fin-channel body.

6. The FinFET claim 1 , further comprising a silicide structure disposed over the epitaxially-grown region.

7. A Fin field effect transistor (FinFET) comprising:

a fin-channel body over a substrate, the substrate having a portion between a first isolation region and a second isolation region;

a gate electrode disposed over the fin-channel body; and

at least one source/drain (S/D) region disposed adjacent to the fin-channel body, the at least one S/D region comprising:

an epitaxially-grown region disposed over the portion of the substrate, wherein the epitaxially-grown region and the portion of the substrate has an interface and a central region of the interface is below a surface of the first isolation region; and

a silicide structure disposed over the epitaxially-grown region,

wherein the first isolation region has a corner where the surface of the first isolation region and a sidewall of the first isolation region intersect, the portion of the substrate has a tip where a surface of the portion of the substrate and a sidewall of the portion of the substrate intersect, and the corner is substantially adjacent to the tip.

8. The FinFET of claim 7 , wherein a distance between the central region of the interface and the surface of the first isolation region is substantially equal to a height of the fin-channel body.

9. The FinFET of claim 7 , wherein the central region of the interface is substantially flat.

10. The FinFET of claim 7 , wherein the epitaxially-grown region is capable of providing a stress to the fin-channel body.

11. A method for forming a Fin field effect transistor (FinFET), the method comprising:

forming a fin over a substrate, and removing at least one end portion of the fin to expose a surface of a portion of the substrate surrounded by first and second isolation regions to form a fin-channel body over the substrate, wherein the first isolation region has a corner where a surface of the first isolation region and a sidewall of the first isolation region intersect, the portion of the substrate has a tip where a surface of the portion of the substrate and a sidewall of the portion of the substrate intersect, and the corner is substantially adjacent to the tip;

forming a gate electrode over the fin-channel body; and

epitaxially growing at least one S/D region from the exposed surface of the portion of the substrate to form the at least one source/drain (S/D) region adjacent to the fin-channel body, the at least one S/D region being substantially free from including any fin structure.

12. The method of claim 11 , further comprising removing a portion of the substrate, wherein a central region of the exposed surface of the portion of the substrate is below a surface of the first isolation region.

13. The method of claim 12 , wherein a distance between the central region of the exposed surface of the substrate and the surface of the first isolation region is substantially equal to a height of the fin-channel body.

14. The method of claim 12 further comprising reflowing the exposed surface of the substrate such that the central region of the exposed surface of the substrate is substantially flat.

15. The method of claim 11 , further comprising:

forming an epitaxial layer over the at least one S/D region; and

salicidating at least one of the epitaxial layer.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Apr 16, 2010
From: LAI, LI-SHYUE; KWOK, TSZ-MEI; YEH, CHIH CHIEH; WANN, CLEMENT HSINGJEN
To: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
Reel/Frame 024245/0795 →
Continuity (2)
Provisional Application 61247756 · Oct 1, 2009
Related Publication 20110079829A1 · Apr 7, 2011