Hybrid orientation accumulation mode GAA CMOSFET
View Patent ↗A hybrid orientation accumulation mode GAA (Gate-All-Around) CMOSFET includes a PMOS region having a first channel, an NMOS region having a second channel and a gate region. The first channel and the second channel have a racetrack-shaped cross section and are formed of p-type Si(110) and n-type Si(100), respectively; the surfaces of the first channel and the second channel are substantially surrounded by the gate region; a buried oxide layer is disposed between the PMOS region and the NMOS region and between the PMOS or NMOS region and the Si substrate to isolate them from one another. The device structure according to the prevent invention is quite simple, compact and highly integrated. In an accumulation mode, current flows through the overall racetrack-shaped channel. The disclosed device results in high carrier mobility. Meanwhile polysilicon gate depletion and short channel effects are prevented, and threshold voltage is increased.
1. A hybrid orientation accumulation mode GAA (Gate-All-Around) CMOSFET (Complementary Metal Oxide Semiconductor Field Effect Transistor) comprising:
a semiconductor substrate;
an NMOS region having a second channel, the NMOS region is stacked up above the semiconductor substrate,
a PMOS region having a first channel, the PMOS region is stacked up above the NMOS region;
a gate region, said gate region surrounds two surfaces of the first channel and the second channel substantially;
the NMOS region and the PMOS region each includes a source region and a drain region located at the two opposite ends of the channel thereof, wherein;
the first channel and the second channel each has a racetrack-shaped cross section having a rectangular central portion and two substantially semicircular end portions contacting the opposite ends of the rectangular central portion, the first channel is stacked up above the second channel and each of them is parallel to the semiconductor substrate, the first channel is formed of p-type Si(110) and the second channel is formed of n-type Si(100);
a first buried oxide layer is disposed between the PMOS region and the NMOS region other than the gate region; and
a second buried oxide layer is disposed between the NMOS region and the semiconductor substrate other than the gate region.
2. The CMOSFET of claim 1 , wherein the source region and the drain region of the PMOS region are formed of heavily doped p-type Si(110) or GeSi.
3. The CMOSFET of claim 1 , wherein the source region and the drain region of the NMOS region are formed of heavily doped n-type Si(100) or SiC.
4. The CMOSFET of claim 1 , wherein the gate region further comprises: a gate dielectric layer substantially surrounding the surfaces of the first channel and the second channel, and a gate electrode material layer substantially surrounding the gate dielectric layer.
5. The CMOSFET of claim 4 , wherein the gate dielectric layer is selected from the group consisting of silicon dioxide, silicon oxynitride, silicon oxycarbide and a hafnium-based high-k material.
6. The CMOSFET of claim 4 , wherein the gate electrode material layer is selected from the group consisting of titanium, nickel, tantalum, tungsten, tantalum nitride, tungsten nitride, titanium nitride, titanium silicide, tungsten silicide, nickel silicide, and a combination thereof.
7. The CMOSFET of claim 1 , wherein the semiconductor substrate is formed of Si.
8. The CMOSFET of claim 1 , wherein the first buried oxide layer and the second buried oxide layer each has a thickness in the range of 10-200 nm.
9. The CMOSFET of claim 1 , wherein the first buried oxide layer and the second buried oxide layer are formed of silicon dioxide.
10. A hybrid orientation accumulation mode GAA (Gate-All-Around) CMOSFET (Complementary Metal Oxide Semiconductor Field Effect Transistor) comprising:
a semiconductor substrate;
a PMOS region having a first channel and is stacked up above the semiconductor substrate;
an NMOS region having a second channel and is stacked up above the PMOS region;
a gate region, said gate region surrounds two surfaces of the first channel and the second channel substantially;
the NMOS region and the PMOS region each includes a source region and a drain region located at the two opposite ends of the channel thereof, wherein;
the first channel and the second channel each has a racetrack-shaped cross section having a rectangular central portion and two substantially semicircular end portions contacting the opposite ends of the rectangular central portion, the second channel is stacked up above the first channel and each of them is parallel to the semiconductor substrate, the first channel is formed of p-type Si(110) and the second channel is formed of n-type Si(100);
a first buried oxide layer is disposed between the PMOS region and the NMOS region other than the gate region; and
a second buried oxide layer is disposed between the PMOS region and the semiconductor substrate other than the gate region.
11. The CMOSFET of claim 10 , wherein the source region and the drain region of the PMOS region are formed of heavily doped p-type Si(110) or GeSi.
12. The CMOSFET of claim 10 , wherein the source region and the drain region of the NMOS region are formed of heavily doped n-type Si(100) or SiC.
13. The CMOSFET of claim 10 , wherein the gate region further comprises: a gate dielectric layer substantially surrounding the surfaces of the first channel and the second channel, and a gate electrode material layer substantially surrounding the gate dielectric layer.
14. The CMOSFET of claim 13 , wherein the gate dielectric layer is selected from the group consisting of silicon dioxide, silicon oxynitride, silicon oxycarbide and a hafnium-based high-k material.
15. The CMOSFET of claim 13 , wherein the gate electrode material layer is selected from the group consisting of titanium, nickel, tantalum, tungsten, tantalum nitride, tungsten nitride, titanium nitride, titanium silicide, tungsten silicide, nickel silicide, and a combination thereof.
16. The CMOSFET of claim 10 , wherein the semiconductor substrate is formed of Si.
17. The CMOSFET of claim 10 , wherein the first buried oxide layer and the second buried oxide layer each has a thickness in the range of 10-200 nm.
18. The CMOSFET of claim 10 , wherein the first buried oxide layer and the second buried oxide layer are formed of silicon dioxide.