IP Library Granted Patent US 8,266,573
Granted Patent B2
US 8,266,573 · App. 12/825,848 · Granted Sep 11, 2012

Method and system for test point insertion

Assignee: Renesas Electronics Corporation
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Quick Facts
Patent No.
US 8,266,573
App. No.
12/825,848
Granted
Sep 11, 2012
Kind
B2
Abstract

It is desired to suppress an increase of the TAT or a repetition of processing in inserting a test circuit on designing. A test point insertion method includes: extracting a plurality of logic cones from a net list; generating an order for the plurality of logic cones based on a connection relation of logic cells in each of the plurality of logic cones; and setting a test point in each of the plurality of logic cones in turn in accordance with the order.

Claims (17)

1. A computer executable test point insertion method comprising:

extracting, with at least one computer, a plurality of logic cones from a net list;

generating an order for the plurality of logic cones based on a connection relation of logic cells in each of the plurality of logic cones; and

setting a test point in each of the plurality of logic cones in turn in accordance with the order;

wherein the order is generated based on a sum of the number of at least one path forming each of the plurality of logic cones and a sum of the number of logic stages of each of the at least one path;

wherein the order is determined by a value generated by a following expression:

( P ( L )×α)×( P ( G )×β)

wherein P (G) is a sum of the number of at least one path forming each of the plurality of logic cones, and P (L) is a sum of the number of logic stages of the at least one path, and α and β are preset coefficients.

2. A computer executable test point insertion method comprising:

extracting, with at least one computer, a plurality of logic cones from a net list;

generating an order for the plurality of logic cones based on a connection relation of logic cells in each of the plurality of logic cones;

setting a test point in each of the plurality of logic cones in turn in accordance with the order; and:

ending the setting when a following inequality is satisfied:

N 1 −N 2≧ N 3

wherein N1 is a preset insertable number of test circuits, N2 is the number of test points inserted by processing the setting at one time, and N3 is the number of test points already set by the setting, and

in the setting, a setting of the test point is repeated in accordance with the order when a following inequality is satisfied:

N 1− N 2<3.

Assignments (2)
CHANGE OF NAME Recorded Oct 26, 2010
From: NEC ELECTRONICS CORPORATION
To: RENESAS ELECTRONICS CORPORATION
Reel/Frame 025191/0916 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jun 30, 2010
From: SASAKI, TSUYOSHI
To: NEC ELECTRONICS CORPORATION
Reel/Frame 024617/0921 →
Priority Claims (1)
JP 2009-172676 · Jul 24, 2009 · national
Continuity (1)
Related Publication 20110022906A1 · Jan 27, 2011