Complementary semiconductor device with a metal oxide layer exclusive to one conductivity type
A method is provided of manufacturing a semiconductor device comprising a first, n-type field effect transistor ( 1 ) and a second, p-type field effect transistor ( 2 ). The method comprises depositing a gate dielectric layer over a substrate; depositing a gate metal layer ( 22 ) over the gate dielectric layer, depositing a solid metal oxide layer ( 15 ) over the gate dielectric layer; removing a portion of the solid metal oxide layer ( 15 ) over an area of the substrate corresponding to the n-type transistor; and completing gate stacks for the n-type and p-type transistors and forming source and drain regions. The invention thus provides a device which is compatible with IC technology and easy to manufacture. The deposition of a solid metal oxide layer provides a simplified manufacturing process, by avoiding the complexity of gas exposure to form an oxide layer.
1. A semiconductor device comprising:
a first, n-type field effect transistor with a first source and drain region and an n-type channel, and a first gate region separated from the n-type channel by a first dielectric region; and
a second, p-type field effect transistor with a second source and drain region and a p-type channel, and a second gate region separated from the p-type channel by a second dielectric region,
wherein the first gate region comprises a first number of layers inclusive of a metal layer, and the second gate region comprises a second number of layers inclusive of the metal layer and an overlying metal oxide layer, and wherein the metal oxide layer is present within the second gate region and not within the first gate region, and the second number of layers in the second gate region is different than the first number of layers in the first gate region.
2. A device as claimed in claim 1 , wherein the metal layer comprises Ru, Mo, W or an alloy thereof.
3. A device as claimed in claim 1 , wherein the portion of the metal layer within the first gate region comprises an implanted chalcogenide.
4. A device as claimed in claim 3 , wherein the chalcogenide is a compound comprising tellurium.
5. A device as claimed in claim 1 , wherein the metal oxide layer comprises a conducting metal oxide.
6. A device as claimed in claim 5 , wherein the conducting metal oxide comprises an oxide of Ru, Mo or W.
7. A device as claimed in claim 1 , wherein each gate region further comprises a work function changing layer between the metal layer and the dielectric layer.
8. A device as claimed in claim 7 , wherein the work function changing layer has a thickness less than 5 nm.
9. A device as claimed in claim 8 , wherein the work function changing layer comprises TiN.
10. A device as claimed in claim 1 , further comprising a cap layer on top of the first and second gate regions.
11. A device as claimed in claim 10 , wherein the cap layer comprises a metal nitride.
12. A method of manufacturing a semiconductor device comprising a first, n-type field effect transistor with a first source and drain region) and an n-type channel, and a first gate region separated from the n-type channel by a first dielectric region, and a second, p-type field effect transistor ( 2 ) with a second source and drain region and a p-type channel, and a second gate region separated from the p-type channel by a second dielectric region, the method comprising:
preparing a substrate to have a semiconductor body of a first type and well of an opposite type;
depositing a gate dielectric layer over the substrate;
depositing a gate metal layer over the gate dielectric layer;
depositing a solid metal oxide layer over the gate dielectric layer;
removing a portion of the solid metal oxide layer over an area of the substrate corresponding to the n-type transistor; and
completing gate stacks for the n-type and p-type transistors and forming source and drain regions, thereby to define one of the transistors over the semiconductor body and the other over the well, and to further define a different number of layers in each of the gate stacks for the n-type and the p-type transistors.
13. A method as claimed in claim 12 , wherein the metal layer comprises Ru, Mo, W or an alloy thereof.
14. A method as claimed in claim 12 , wherein a mask is deposited over the metal oxide layer and is used for etching of the metal oxide layer to remove the portion of the solid metal oxide layer.
15. A method as claimed in claim 12 , further comprising implanting a chalcogenide into the metal layer over an area of the substrate corresponding to the n-type transistor.
16. A method as claimed in claim 15 , wherein the mask is also used as a shield for the implantation.
17. A method as claimed in claim 15 wherein the chalcogenide is a compound comprising tellurium.
18. A method as claimed in claim 12 , wherein the metal oxide layer comprises a conducting metal oxide.
19. A method as claimed in claim 18 , wherein the conducting metal oxide comprises an oxide of Ru, Mo or W.
20. A method as claimed in claim 12 , further comprising depositing a work function changing layer on the dielectric layer before deposition of the metal layer.
21. A method as claimed in claim 20 , wherein the work function changing layer is deposited to a thickness of less than 5 nm.
22. A method as claimed in claim 21 , wherein the work function changing layer comprises TiN.
23. A method as claimed in claim 12 , wherein completing the gate stacks comprises depositing a cap layer on top of the first and second gate regions.