Method of constructing a semiconductor device and structure
A method of manufacturing a semiconductor device, the method including, providing a first monocrystalline layer including semiconductor regions, overlaying the first monocrystalline layer with an isolation layer, transferring a second monocrystalline layer comprising semiconductor regions to overlay the isolation layer, wherein the first monocrystalline layer and the second monocrystalline layer are formed from substantially different crystal materials; and subsequently etching the second monocrystalline layer as part of forming at least one transistor in the second monocrystalline layer.
1. A method of manufacturing a semiconductor device, the method comprising:
providing a first monocrystalline layer comprising first semiconductor regions;
overlaying said first monocrystalline layer with at least one metal layer comprising aluminum or copper;
transferring a second monocrystalline layer comprising second semiconductor regions to a carrier;
annealing said second monocrystalline layer while on said carrier as part of forming at least one transistor on said second monocrystalline layer; and
after said annealing, transferring said second monocrystalline layer to overlay said metal layer;
wherein said annealing comprises a thermal anneal which is greater than 400 degrees Centigrade and wherein said first and second semiconductor regions comprise ion implanted and activated dopants.
2. The method according to claim 1 wherein said at least one transistor comprises at least one p-type transistor and at least one n-type transistor.
3. The method according to claim 1 wherein said at least one transistor is one of:
(i) a recessed-channel transistor (RCAT);
(ii) a junction-less transistor;
(iii) a replacement-gate transistor;
(iv) a thin-side-up transistor;
(v) a double gate transistor;
(vi) a horizontally oriented transistor;
(vii) a finfet type transistor;
(viii) a Dopant Segregated Schottky (DSS-Schottky) transistor; or
(ix) a trench MOSFET transistor.
4. The method according to claim 1 wherein said forming comprises etching.
5. The method according to claim 1 , further comprising:
forming at least one heat removal connection that does not conduct electricity.
6. The method according to claim 1 wherein said annealing comprises one of an ultrasound annealing or an optical annealing or microwave treatments.
7. The method according to claim 1 wherein said semiconductor device is an field programmable gate array (FPGA).
8. The method according to claim 1 wherein said semiconductor device is a gate array.
9. The method according to claim 1 wherein said annealing comprises one of a vacuum, a pressure greater than 760 torr, oxidizing atmospheres, or reducing atmospheres.
10. The method according to claim 1 wherein a debond/release agent of said transferring of said second monocrystalline layer to overlay said metal layer comprises hydrofluoric acid.
11. The method according to claim 1 wherein said second monocrystalline layer comprises silicon.
12. The method according to claim 1 wherein said first monocrystalline layer comprises silicon.