IP Library Granted Patent US 8,273,628
Granted Patent B2
US 8,273,628 · App. 12/718,641 · Granted Sep 25, 2012

Semiconductor device manufacturing method including exposing electrode layers into a hole

Assignee: Kabushiki Kaisha Toshiba
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Quick Facts
Patent No.
US 8,273,628
App. No.
12/718,641
Granted
Sep 25, 2012
Kind
B2
Abstract

A semiconductor device manufacturing method includes: alternately stacking a plurality of insulating layers and electrode layers; forming a hole penetrating through a multilayer body of the insulating layers and the electrode layers; forming a conductive film on an inner wall of the hole; anisotropically etching the conductive film to selectively leave the conductive film on a sidewall of the hole; altering the conductive film into an insulator by heat treatment; and removing the insulator covering the electrode layers to expose the electrode layers into the hole.

Claims (35)

1. A semiconductor device manufacturing method comprising:

alternately stacking a plurality of insulating layers and electrode layers;

forming a hole penetrating through a multilayer body of the insulating layers and the electrode layers;

forming a conductive film on an inner wall of the hole;

anisotropically etching the conductive film to selectively leave the conductive film on a sidewall of the hole;

altering the conductive film into an insulator by heat treatment; and

removing the insulator covering the electrode layers to expose the electrode layers into the hole.

2. The method according to claim 1 , wherein the conductive film is altered into the insulator by thermal oxidation.

3. The method according to claim 1 , wherein the electrode layers and the conductive film are made of the same material.

4. The method according to claim 3 , wherein the electrode layers and the conductive film contain silicon.

5. The method according to claim 1 , wherein the insulating layers are silicon oxide layers.

6. The method according to claim 1 , wherein the conductive film at bottom of the hole is removed by the anisotropic etching.

7. The method according to claim 1 , wherein a thickness of the conductive film left on the sidewall of the hole is relatively thinner on a lower portion of the hole than on an upper portion of the hole.

8. The method according to claim 2 , wherein by the heat treatment, oxidation is advanced by at least a thickness of the conductive film.

9. The method according to claim 2 , wherein the thermal oxidation is advanced also toward the electrode layers in a portion of the conductive film opposed to the electrode layers.

10. The method according to claim 2 , wherein the thermal oxidation forms a thermally oxidized portion expanded in volume into the hole relative to the conductive film.

11. The method according to claim 1 , wherein the insulator is removed by etching.

12. The method according to claim 11 , wherein in the etching for removing the insulator, the insulating layers are overetched in a direction expanding the hole relative to end surfaces of the electrode layers exposed into the hole.

13. The method according to claim 1 , further comprising:

after exposing the electrode layers into the hole, forming an insulating film including a charge storage layer on the sidewall of the hole; and

forming a semiconductor layer inside the insulating film in the hole.

14. The method according to claim 13 , wherein the forming the insulating film includes:

forming a first silicon oxide film on the sidewall of the hole;

forming a silicon nitride film as the charge storage layer inside the first silicon oxide film; and

forming a second silicon oxide film inside the silicon nitride film.

15. A semiconductor device manufacturing method comprising:

forming a recess in a conductive layer;

burying a sacrificial film in the recess;

alternately stacking a plurality of insulating layers and electrode layers on the conductive layer having the sacrificial film buried therein;

forming a hole penetrating through a multilayer body of the insulating layers and the electrode layers;

forming a conductive film on an inner wall of the hole;

anisotropically etching the conductive film to selectively leave the conductive film on a sidewall of the hole;

altering the conductive film into an insulator by heat treatment;

removing the insulator covering the electrode layers to expose the electrode layers into the hole; and

removing the sacrificial film in the recess through the hole to connect the hole exposing the electrode layers to the recess.

Assignments (5)
CHANGE OF NAME AND ADDRESS Recorded Jan 22, 2021
From: K.K. PANGEA
To: TOSHIBA MEMORY CORPORATION
Reel/Frame 055669/0401 →
MERGER Recorded Jan 22, 2021
From: TOSHIBA MEMORY CORPORATION
To: K.K. PANGEA
Reel/Frame 055659/0471 →
CHANGE OF NAME AND ADDRESS Recorded Jan 22, 2021
From: TOSHIBA MEMORY CORPORATION
To: KIOXIA CORPORATION
Reel/Frame 055669/0001 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Aug 24, 2017
From: KABUSHIKI KAISHA TOSHIBA
To: TOSHIBA MEMORY CORPORATION
Reel/Frame 043709/0035 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Mar 10, 2010
From: YAHASHI, KATSUNORI
To: KABUSHIKI KAISHA TOSHIBA
Reel/Frame 024059/0946 →
Priority Claims (1)
JP 2009-194028 · Aug 25, 2009 · national
Continuity (1)
Related Publication 20110049607A1 · Mar 3, 2011