Vertically-oriented semiconductor selection device providing high drive current in cross-point array memory
A vertical semiconductor material mesa upstanding from a semiconductor base that forms a conductive channel between first and second doped regions. The first doped region is electrically coupled to one or more first silicide layers on the surface of the base. The second doped region is electrically coupled to one of a plurality of second silicide layers on the upper surface of the mesa. A gate conductor is provided on one or more sidewalls of the mesa.
1. A transistor structure comprising:
a semiconductor material base;
a semiconductor material mesa upstanding from said base;
a plurality of electrically isolated first silicide material elements on a top surface of said mesa;
a second silicide material element supported on said semiconductor material base at least at a first side of said mesa for supplying an electrical connection to said mesa;
first and second regions respectively coupled to the first and second silicide material elements, the first and second regions being doped to a first conduction type and one or more channel regions between the first and second regions being doped to a second conduction type;
a first mesa sidewall gate structure provided on said first side of said mesa and comprising a gate insulator material and an overlying gate conductor, said first mesa sidewall gate structure being operative to control current flow through said channel regions between said second silicide material element and each of said first silicide material elements through said mesa; and
a plurality of operative electrical devices respectively connected to each of said first silicide elements.
2. A transistor structure as in claim 1 further comprising:
a third silicide material element supported on said semiconductor material base at a second side of said mesa opposite said first side; and
a second mesa sidewall gate structure provided on said second side of said mesa and comprising a gate insulator material and an overlying gate conductor, said second mesa sidewall gate structure being operative to control with said first mesa sidewall gate structure current flow between each of said first silicide material elements and said second material element and each of said first silicide material elements and said third silicide material element through said mesa.
3. A transistor structure comprising:
a semiconductor material base;
a semiconductor material mesa upstanding from said base;
a plurality of electrically isolated first silicide material elements on a top surface of said mesa;
a second silicide material element supported on said semiconductor material base at least at a first side of said mesa for supplying an electrical connection to said mesa;
first and second regions respectively coupled to the first and second silicide material elements, the first and second regions being doped to a first conduction type and one or more channel regions between the first and second regions being doped to a second conduction type;
a first mesa sidewall gate structure provided on said first side of said mesa and comprising a gate insulator material and an overlying gate conductor, said first mesa sidewall gate structure being operative to control current flow through said channel regions between said second silicide material element and each of said first silicide material elements through said mesa;
a third silicide material element supported on said semiconductor material base at a second side of said mesa opposite said first side; and
a second mesa sidewall gate structure provided on said second side of said mesa and comprising a gate insulator material and an overlying gate conductor, said second mesa sidewall gate structure being operative to control with said first mesa sidewall gate structure current flow between each of said first silicide material elements and said second material element and each of said first silicide material elements and said third silicide material element through said mesa; and
a recess in the top surface of each mesa between an adjacent pair of first silicide material elements.
4. A transistor structure comprising:
a semiconductor material base;
a semiconductor material mesa upstanding from said base;
a plurality of electrically isolated first silicide material elements on a top surface of said mesa;
a second silicide material element supported on said semiconductor material base at least at a first side of said mesa for supplying an electrical connection to said mesa;
first and second regions respectively coupled to the first and second silicide material elements, the first and second regions being doped to a first conduction type and one or more channel regions between the first and second regions being doped to a second conduction type;
a first mesa sidewall gate structure provided on said first side of said mesa and comprising a gate insulator material and an overlying gate conductor, said first mesa sidewall gate structure being operative to control current flow through said channel regions between said second silicide material element and each of said first silicide material elements through said mesa;
a plurality of parallel upstanding mesas, wherein each of said upstanding mesas comprises a plurality of first silicide elements spaced along a top mesa surface;
a plurality of second silicide elements supported on said semiconductor material base and extending along at least a first side of a respective mesa; and
a plurality of first mesa sidewall gate structures respectively provided on a first side of a mesa and comprising a gate insulator material and an overlying gate conductor, each first mesa sidewall gate structure being operative to control current flow between a respective second silicide element and a plurality of spaced first silicide elements associated with a respective mesa.
5. A transistor structure as in claim 4 , further comprising a plurality of operative electrical devices respectively connected to each of said first silicide elements.
6. A transistor structure comprising:
a semiconductor material base;
a semiconductor material mesa upstanding from said base;
a plurality of electrically isolated first silicide material elements on a top surface of said mesa;
a second silicide material element supported on said semiconductor material base at least at a first side of said mesa for supplying an electrical connection to said mesa;
first and second regions respectively coupled to the first and second silicide material elements, the first and second regions being doped to a first conduction type and one or more channel regions between the first and second regions being doped to a second conduction type;
a first mesa sidewall gate structure provided on said first side of said mesa and comprising a gate insulator material and an overlying gate conductor, said first mesa sidewall gate structure being operative to control current flow through said channel regions between said second silicide material element and each of said first silicide material elements through said mesa;
a plurality of mesas comprising a first linearly aligned group of mesas and a second linearly aligned group of mesas, each of said first and second linearly aligned group of mesas comprising at least a first and second mesa within the group;
a plurality of first silicide elements spaced along a top surface of each mesa, a plurality of second silicide elements supported on said semiconductor material base and extending along at least a first side of said at least first and second mesa of a group; and
a first mesa sidewall gate structure providing on said first side of each said at least first and second mesa of a group and comprising a gate insulator material and an overlying gate conductor, each said first mesa sidewall gate structure being operative to control current flow between a second silicide element common to a group of mesas and a plurality of spaced first silicide elements on the mesas of a group.
7. A memory structure comprising:
a plurality of vertical transistors, each transistor comprising:
a semiconductor material projection extending from a semiconductor material base;
a plurality of first conductors provided on an upper surface of said projection, the first conductors being formed of silicide;
a second conductor provided on said base and adjacent to at least a first sidewall of said projection, the second conductor being formed of silicide; and
a first gate structure provided on said first sidewall of said projection for gating current flow between said first and second conductors, at least two of said vertical transistors being provided on each said projection;
a plurality of memory cells each having a first side connected to a respective first conductor of said at least two vertical transistors; and
a plurality of third conductors respectively connected to a second side of said plurality of memory cells.
8. A memory structure as in claim 7 , further comprising:
a plurality of linearly extending semiconductor material projections, each containing a plurality of said vertical transistors;
a plurality of said first conductors spaced along a top surface of each projection, each being associated with a respective vertical transistor;
a first plurality of said second conductors each extending along at least a first sidewall of a respective semiconductor material projection;
a gate structure extending along said first sidewall of each projection for commonly gating the first and second conductors associated with each projection;
a respective memory cell connected to each of said first conductors; and
wherein said plurality of third conductors each respectively connect to a second side of a plurality of memory cells connected to vertical transistors in different semiconductor material projections.
9. A memory structure as in claim 8 , wherein said plurality of linearly extending semiconductor material projections are arranged in a plurality of parallel linearly extending lines where each line is formed of a continuous semiconductor material projection.
10. A memory structure as in claim 8 , wherein said plurality of linearly extending semiconductor material projections are arranged in parallel spaced lines of projections where a plurality of spaced semiconductor material projections are provided in each said line.
11. A memory structure as in claim 7 , further comprising a plurality of fourth conductors provided on said semiconductor base adjacent to at least a second sidewall of a respective projection, and a second gate structure provided on said second sidewall of said respective projection for gating current flow between said first and fourth conductors.
12. A memory structure as in claim 11 , wherein said first and second gate structures are interconnected to function as a single gate structure.
13. A memory structure as in claim 10 , wherein said second conductor extends over said semiconductor base material in areas between projections provided in a line of spaced projections.
14. A memory structure as in claim 13 , wherein said plurality of spaced projections in each line are organized so that spaces between projections on adjacent lines are shifted in relation to one another.
15. A memory structure as in claim 11 , wherein said second and fourth conductors are electrically interconnected.
16. A memory structure as in claim 11 , wherein second and fourth conductors provided on opposite sides of a respective projection are electrically interconnected.
17. A memory structure as in claim 16 , wherein said second and fourth conductors are interconnected in areas between projections provided in a line of spaced projections.
18. An integrated circuit structure comprising:
a semiconductor substrate containing a plurality of trenches therein defining a plurality of upstanding semiconductor mesas arranged in a pattern of a plurality of linearly extending parallel lines of mesas;
a plurality of spaced first silicide material areas on an upper surface of each of said mesas;
a second silicide material on said substrate adjacent to at least a first sidewall of each of said mesas; and
a plurality of gate structures respectively provided at least on said first sidewalls of said mesas arranged in each said line of mesas, such that each of said mesas in a line share a common gate structure at said first sidewall.
19. An integrated circuit structure as in claim 18 , wherein the second silicide material on said substrate is an electrically continuous silicide structure.
20. An integrated circuit structure as in claim 18 , wherein said second silicide material on said substrate is also adjacent a second sidewall of said mesa structures, and wherein said plurality of gate structures are provided on said second sidewalls of said mesas and arranged in each said line such that each of said mesas in a line share a common gate structure at said second sidewall.
21. An integrated circuit structure as in claim 18 , wherein each extending mesa line comprises a continuous mesa structure.
22. An integrated circuit structure as in claim 18 , wherein each extending mesa line comprises a plurality of spaced mesas.
23. An integrated circuit structure as in claim 22 , wherein said second silicide material is further provided on said semiconductor substrate in areas between said plurality of spaced mesas.
24. An integrated circuit structure as in claim 20 , wherein each extending mesa line comprises a continuous mesa structure.
25. An integrated circuit structure as in claim 20 , wherein each extending mesa line comprises a plurality of spaced mesas.
26. An integrated circuit structure as in claim 25 , wherein said second silicide material is further provided on said semiconductor substrate in areas between said plurality of spaced mesas.