Method for fabricating a semiconductor memory device having a buried word line structure
A method for fabricating a semiconductor apparatus including a buried gate removes factors deteriorating the operational reliability of the semiconductor device such as the electrical connection between a contact and a word line, and increases a processing margin when forming the contact disposed on a source/drain region. The method includes forming a recess in a semiconductor substrate, forming a gate in a lower portion of the recess, forming a first insulation layer over the gate, growing silicon over the first insulation layer in the recess, and depositing a second insulation layer over the semiconductor substrate and in the remaining portion of the recess.
1. A method for fabricating a semiconductor apparatus, the method comprising:
forming a recess in a semiconductor substrate, the recess having a lower portion and an upper portion;
forming a gate in the lower portion of the recess;
forming a first insulation layer over the gate and in the upper portion of the recess;
forming a silicon growth region using an epitaxial growth method, the silicon growth region having a lateral extension, the lateral extension being provided over the first insulation layer in the recess and extending laterally in the recess from the semiconductor substrate through a sidewall of the recess; and
forming a second insulating layer on the first insulating layer.
2. The method of claim 1 , where the step of forming the silicon growth region comprises:
cleaning the sidewall of the recess to expose a silicon surface of the sidewall of the recess; and
selectively growing silicon material on the exposed silicon surface.
3. The method of claim 1 , wherein the step of forming the gate in the lower portion of the recess comprises:
depositing conductive material in the recess, the conductive material filling the lower portion and the upper portion of the recess;
performing an etch-back process to remove the conductive material in the upper portion of the recess; and
cleaning the upper portion of the recess.
4. The method of claim 1 , further comprises depositing a barrier metal layer in the recess, the barrier metal layer being provided between the gate and the surface of the recess.
5. The method of claim 4 , wherein the barrier metal layer includes tungsten nitride, and the gate includes tungsten.
6. The method of claim 1 , wherein the step of forming of the first insulation layer over the gate comprises:
depositing an insulating material over the gate;
removing the insulating material using an etch-back process until the insulating material is provided with a given thickness, thereby forming the first insulation layer; and
cleaning the recess after the etch-back process.
7. The method of claim 1 , wherein the first insulation layer includes an oxide layer or a nitride layer, and a thickness of the first insulation layer is at least 10 Å.
8. The method of claim 1 , wherein a lowermost surface of the gate extends vertically downward to 1100 Å to 1300 Å from an uppermost surface of the semiconductor substrate, and an uppermost surface of the gate vertically extends downward to approximately 300 Å to approximately 400 Å from the uppermost surface of the semiconductor substrate.
9. The method of claim 1 , wherein the lateral extension of the silicon growth region is configured to reduce a width of an opening of the recess.
10. A semiconductor device, comprising:
a gate formed in a recess that is formed in a semiconductor substrate;
an insulation layer formed over the gate in the recess;
a silicon growth region obtained by an epitaxial growth method, the silicon growth region having a lateral extension provided over the insulation layer and extending laterally into the recess from the semiconductor substrate through a sidewall of the recess: and
a second insulating layer formed on the insulating layer.
11. The semiconductor device of claim 10 , wherein a thickness of the insulation layer is at least 10 Å.
12. The semiconductor device of claim 10 , wherein the recess has a depth of 1100 Å to 1300 Å, and an uppermost surface of the gate is provided at a depth of 300 Å to 400 Å.
13. The semiconductor device of claim 10 , further comprising a barrier metal layer provided between the gate and a surface of the recess, wherein the gate includes tungsten and the barrier metal layer includes tungsten nitride.
14. The semiconductor apparatus of claim 10 , wherein the lateral extension of the silicon growth region is configured to reduce a line width of the recess by up to 80% of the line width.