IP Library Granted Patent US 8,279,409
Granted Patent B1
US 8,279,409 · App. 12/536,425 · Granted Oct 2, 2012

System and method for calibrating a lithography model

Assignee: Cadence Design Systems, Inc.
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Quick Facts
Patent No.
US 8,279,409
App. No.
12/536,425
Granted
Oct 2, 2012
Kind
B1
Abstract

The present invention provides a method for calibrating a computational model of a lithography process by calculating a demerit function using an intensity measurement at a location of a wafer; and calibrating the lithography model or a mask making model by determining values of parameters of the computational model using the calculated demerit function. The method may also use a second demerit function that is defined by the sum of squares of differences between a simulated and measured critical dimensions of a feature on the wafer.

Claims (48)

1. A method for calibrating a model of a photolithography process, comprising:

providing a computational model of a photolithography process, the computational model having an adjustable parameter;

printing a first pattern with the photolithography process as a printed pattern;

measuring an aspect of the printed pattern;

using the computational model to calculate an image intensity at a location determined according to the measured aspect;

minimizing a first cost function that comprises a first difference between the calculated image intensity and an intensity threshold;

calculating a second cost function comprising a second difference between a measured critical dimension of the printed pattern and a critical dimension simulated by the computational model;

minimizing the first cost function with respect to a model parameter;

determining if the computational model predicts that a portion of a first pattern will not print;

removing from a definition of the second cost function, the critical dimension of the portion of the first pattern that will not print; and

minimizing the second cost function with respect to the model parameter.

2. The method of claim 1 , wherein the photolithography process comprises projecting an optical image onto a semiconductor wafer.

3. The method of claim 1 , wherein the photolithography process comprises projecting an electron-beam image exposing a resist on a semiconductor wafer.

4. The method of claim 1 , wherein the photolithography process comprises scanning a switched electron beam exposing a resist on a semiconductor wafer.

5. The method of claim 1 , wherein the photolithography process comprises an electron beam exposing a resist on a photomask.

6. A computer program product having instructions embedded in a non-transitory computer useable medium, the instructions configured to cause a processor to perform the operations of:

providing a computational model of a photolithography process, the computational model having an adjustable parameter;

printing a first pattern with the photolithography process as a printed pattern;

measuring an aspect of the printed pattern;

using the computational model to calculate an image intensity at a location determined according to the measured aspect;

minimizing a first cost function that comprises a first difference between the calculated image intensity and an intensity threshold;

calculating a second cost function comprising a second difference between a measured critical dimension of the printed pattern and a critical dimension simulated by the computational model;

minimizing the first cost function with respect to a model parameter;

determining if the computational model predicts that a portion of a first pattern will not print;

removing from a definition of the second cost function, the critical dimension of the portion of the first pattern that will not print; and

minimizing the second cost function with respect to the model parameter.

7. The computer program product of claim 6 , wherein the photolithography process comprises projecting an optical image onto a semiconductor wafer.

8. The computer program product of claim 6 , wherein the photolithography process comprises projecting an electron-beam image exposing a resist on a semiconductor wafer.

9. The computer program product of claim 6 , wherein the photolithography process comprises scanning a switched electron beam exposing a resist on a semiconductor wafer.

10. The computer program product of claim 6 , wherein the photolithography process comprises an electron beam exposing a resist on a photomask.

11. A computer-aided design tool configured to calibrate a model of photolithography process, comprising:

a processor;

a memory connected to the processor; and

a non-transitory computer readable medium having instructions embedded therein, the instructions configured to cause the processor to perform the operations of:

providing a computational model of a photolithography process, the computational model having an adjustable parameter;

printing a first pattern with the photolithography process as a printed pattern;

measuring an aspect of the printed pattern;

using the computational model to calculate an image intensity at a location determined according to the measured aspect;

minimizing a first cost function that comprises a first difference between the calculated image intensity and an intensity threshold;

calculating a second cost function comprising a second difference between a measured critical dimension of the printed pattern and a critical dimension simulated by the computational model;

minimizing the first cost function with respect to a model parameter;

determining if the computational model predicts that a portion of a first pattern will not print;

removing from a definition of the second cost function, the critical dimension of the portion of the first pattern that will not print; and

minimizing the second cost function with respect to the model parameter.

12. The computer-aided design tool of claim 11 , wherein the photolithography process comprises projecting an optical image onto a semiconductor wafer.

13. The computer-aided design tool of claim 11 wherein the photolithography process comprises projecting an electron-beam image exposing a resist on a semiconductor wafer.

14. The computer-aided design tool of claim 11 , wherein the photolithography process comprises scanning a switched electron beam exposing a resist on a semiconductor wafer.

15. The computer-aided design tool of claim 11 , wherein the photolithography process comprises an electron beam exposing a resist on a photomask.

Assignments (2)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Mar 14, 2025
From: CADENCE DESIGN SYSTEMS, INC.
To: SILVACO, INC.
Reel/Frame 070519/0972 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Oct 21, 2009
From: SEZGINER, ABDURRAHMAN; HUANG, HSU-TING; CARRERO, JESUS ORSELY; CHOW, TATUNG; CHUYESHOV, KOSTYANTYN; PERCIN, GOKHAN
To: CADENCE DESIGN SYSTEMS, INC.
Reel/Frame 023405/0341 →