IP Library › Granted Patent US 8,279,645
Granted Patent B2
US 8,279,645 · App. 13/093,629 · Granted Oct 2, 2012

Synchronizing frequency and phase of multiple variable frequency power converters

Assignee: Fairchild Semiconductor Corporation
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Quick Facts
Patent No.
US 8,279,645
App. No.
13/093,629
Granted
Oct 2, 2012
Kind
B2
Abstract

In an embodiment, a power converter system includes a plurality of variable frequency power converters and a plurality of synchronization circuits. Each variable frequency power converter has a switching frequency. Each synchronization circuit is associated with a respective one of the plurality of variable frequency power converters. A control circuit is coupled to and coordinates the plurality of synchronization circuits. The plurality of synchronization circuits and the control circuit are operable to synchronize the switching frequencies of the variable frequency power converters to each other. Each synchronization circuit is operable to: receive a first input signal indicative of the beginning of a switching period for the associated variable frequency power converter; receive a second input signal indicative of the end of the switching period for the associated variable frequency power converter; generate a first output signal for directing a pulse width modulation of the associated variable frequency power converter; and generate a second output signal for coordinating a phase relationship with another variable frequency power converter in the system.

Claims (33)

1. A semiconductor device for synchronizing a plurality of variable frequency power converters, each variable frequency power converter having a switching frequency, the semiconductor device comprising:

a plurality of synchronization circuits, each synchronization circuit corresponding to a respective one of the plurality of variable frequency power converters; and

a control circuit coupled to and coordinating the plurality of synchronization circuits;

wherein the plurality of synchronization circuits and the control circuit are operable to synchronize the switching frequencies of the variable frequency power converters to each other;

wherein each synchronization circuit is operable to:

receive a first input signal indicative of the beginning of a switching period for the corresponding variable frequency power converter;

receive a second input signal indicative of the end of the switching period for the corresponding variable frequency power converter;

generate a first output signal for directing a pulse width modulation of the corresponding variable frequency power converter; and

generate a synchronization control signal for coordinating a phase relationship with another one of the plurality of synchronization circuits.

2. The semiconductor device of claim 1 , further comprising a plurality of pulse width modulators, wherein each pulse width modulator corresponds to one of the synchronization circuits and is configured to receive the first output signal from the corresponding synchronization circuit and to drive a switching device of the corresponding variable frequency power converter for delivering power at a load.

3. The semiconductor device of claim 1 wherein for at least some of the plurality of synchronization circuits the first output signal is generated in response to the first input signal indicative of the beginning of a switching period for the corresponding variable frequency power converter and one of the synchronization control signals generated by another synchronization circuit.

4. The semiconductor device of claim 1 wherein the plurality of synchronization circuits are coupled in a daisy-chain loop configuration.

5. The semiconductor device of claim 4 wherein each of the plurality of synchronization circuits receives the synchronization control signal generated by another one of the synchronization circuits in the daisy-chain loop configuration.

6. The semiconductor device of claim 1 wherein each synchronization circuit is operable to measure a natural switching frequency of the corresponding variable frequency power converter.

7. The semiconductor device of claim 1 wherein the plurality of synchronization circuits are configured to use the longest switching period of any of the plurality of variable frequency power converters as the switching period for all of the variable frequency power converters.

8. The semiconductor device of claim 1 wherein the plurality of synchronization circuits and the control circuit are operable to calculate a switching period to be used by all of the variable frequency power converters.

9. The semiconductor device of claim 1 , wherein the plurality of synchronization circuits and the control circuit are implemented in a single semiconductor die.

10. The semiconductor device of claim 9 , further comprising a digital clock providing a digital clock signal to each of the synchronization circuits.

11. A semiconductor device for synchronizing first through Nth variable frequency power converters, each variable frequency power converter having a switching frequency, the semiconductor device comprising:

first through Nth synchronization circuits coupled in a daisy-chain loop configuration, each synchronization circuit corresponding to a respective one of the first through Nth variable frequency power converters;

wherein the first through Nth synchronization circuits are operable to support the synchronizing of the switching frequencies of the first through Nth variable frequency power converters to each other;

wherein each first through Nth synchronization circuit is operable to:

receive a Begin Period input signal indicative of the beginning of a switching period for the corresponding variable frequency power converter;

receive an End Period input signal indicative of the end of the switching period for the corresponding variable frequency power converter;

generate a Start PWM output signal for directing a pulse width modulation of the corresponding variable frequency power converter; and

receive a Sync In input signal and generate a Sync Out output signal for coordinating phase relationships between the first through Nth synchronization circuits.

12. The semiconductor device of claim 11 comprising a control circuit coupled to and coordinating the first through Nth synchronization circuits.

13. The semiconductor device of claim 12 wherein the first through Nth synchronization circuits and the control circuit are operable to calculate a switching period to be used by all of the variable frequency power converters in the system.

14. The semiconductor device of claim 11 , further comprising a plurality of pulse width modulators, wherein each pulse width modulator corresponds to one of the first through Nth synchronization circuits and is configured to receive the Start PWM output signal from the corresponding synchronization circuit and to drive a switching device of the corresponding variable frequency power converter for delivering power at a load.

15. The semiconductor device of claim 11 wherein each of the first through Nth synchronization circuits is operable to measure a natural switching frequency of the corresponding variable frequency power converter.

16. The semiconductor device of claim 11 wherein the first through Nth synchronization circuits are configured to use the longest switching period of any of the first through Nth variable frequency power converters as the switching period for all of the variable frequency power converters.

17. The semiconductor device of claim 11 , wherein the first through Nth synchronization circuits are implemented in a single semiconductor die.

18. The semiconductor device of claim 17 , further comprising a digital clock providing a digital clock signal to each of the first through Nth synchronization circuits.

Assignments (6)
RELEASE OF SECURITY INTEREST IN PATENTS RECORDED AT REEL 058871, FRAME 0799 Recorded Jun 23, 2023
From: DEUTSCHE BANK AG NEW YORK BRANCH, AS COLLATERAL AGENT
To: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC; FAIRCHILD SEMICONDUCTOR CORPORATION
Reel/Frame 065653/0001 →
RELEASE OF SECURITY INTEREST IN PATENTS RECORDED AT REEL 040075, FRAME 0644 Recorded Jun 22, 2023
From: DEUTSCHE BANK AG NEW YORK BRANCH, AS COLLATERAL AGENT
To: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC; FAIRCHILD SEMICONDUCTOR CORPORATION
Reel/Frame 064070/0536 →
SECURITY INTEREST Recorded Nov 12, 2021
From: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
To: DEUTSCHE BANK AG NEW YORK BRANCH, AS COLLATERAL AGENT
Reel/Frame 058871/0799 →
RELEASE OF SECURITY INTEREST Recorded Oct 28, 2021
From: DEUTSCHE BANK AG NEW YORK BRANCH
To: FAIRCHILD SEMICONDUCTOR CORPORATION
Reel/Frame 057969/0206 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Aug 3, 2021
From: FAIRCHILD SEMICONDUCTOR CORPORATION
To: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
Reel/Frame 057694/0374 →
PATENT SECURITY AGREEMENT Recorded Sep 19, 2016
From: FAIRCHILD SEMICONDUCTOR CORPORATION
To: DEUTSCHE BANK AG NEW YORK BRANCH, AS COLLATERAL AGENT
Reel/Frame 040075/0644 →
Continuity (3)
Continuation 12361419 · Jan 28, 2009
Provisional Application 61125793 · Apr 29, 2008
Related Publication 20110199797A1 · Aug 18, 2011