Bus bridge and method for interfacing out-of-order bus and multiple ordered buses
A method for interfacing an out-of-order bus and multiple ordered buses and a bus bridge. The bus bridge includes multiple ordered bus interfaces, where each ordered bus interface is coupled to an ordered bus. A flow control logic circuit is coupled to the out-of-order bus and to the multiple ordered bus interfaces. The flow control logic circuit controls a flow of transaction requests between the out-of-order bus and each of the ordered buses interfaces. The flow control logic circuit includes an updating circuit for updating dependency resolution attributes and data readiness attributes associated with transaction requests, and a shared memory unit for storing the dependency resolution attributes, the data readiness attributes and the transaction requests where the transaction requests are destined to the ordered buses. A managing circuit, coupled to the shared memory unit and to the multiple ordered bus interfaces, is used to determine a readiness of each transaction request based on a dependency resolution attribute and a data readiness attribute associated with the transaction request, and for managing a dequeueing of ready transaction requests to the ordered bus interfaces based on an availability of the ordered bus interfaces.
1. A bus bridge, comprising:
multiple ordered bus interfaces, wherein each ordered bus interface is coupled to an ordered bus; and
a flow control logic circuit, coupled to the out-of-order bus and the multiple ordered bus interfaces, for controlling a flow of transaction requests between the out-of-order bus and each of the ordered bus interfaces;
wherein the flow control logic circuit includes:
an updating circuit, for updating dependency resolution attributes and data readiness attributes associated with transaction requests;
a shared memory unit, for storing the dependency resolution attributes, the data readiness attributes and the transaction requests, wherein the transaction requests are destined to the ordered buses; and
a managing circuit, coupled to the shared memory unit and to the multiple ordered bus interfaces, for determining a readiness of each transaction request based on a dependency resolution attribute and a data readiness attribute associated with the transaction request, and for managing a dequeueing of ready transaction requests to the ordered bus interfaces based on an availability of the ordered bus interfaces.
2. The bus bridge according to claim 1 , wherein the managing circuit comprises a transaction request arbiter for arbitrating between ready transaction requests that are associated with different ordered buses.
3. The bus bridge according to claim 1 , further comprising a monitor for monitoring a level of fullness of the shared memory unit and for sending, to an out-of-order bus controller, an availability indicator that is indicative of an ability of the shared memory to receive ready transaction requests.
4. The bus bridge according to claim 1 , wherein the updating circuit is arranged to receive a data readiness indicator that is indicative of an availability of data that corresponds to a relevant transaction cycle and is destined to a relevant ordered bus, to search in the shared memory unit for a matching write transaction request, and to update the data readiness attribute associated with the matching write transaction request.
5. The bus bridge according to claim 1 , wherein the updating circuit is arranged to update the data readiness attribute of a read transaction request to indicate that the data of the read transaction request is ready.
6. The bus bridge according to claim 1 , wherein the flow control logic circuit is arranged to control a flow of transaction request responses from the ordered bus interfaces to the out-of-order bus interface; and wherein the flow control logic circuit further comprises a transaction response arbiter for arbitrating between transaction request responses that originate from different ordered bus interfaces.
7. The bus bridge according to claim 1 , wherein the shared memory unit is arranged to store a maximal number of transaction requests and each ordered bus interface is arranged to store a maximal number of ready transaction requests; and wherein the maximal number of transaction requests is greater than the maximal number of ready transaction requests.
8. The bus bridge according to claim 1 , wherein the flow control logic circuit further comprises a tracking circuit for storing, for each ordered bus, a last transaction cycle identifier and a pending transaction request indicator, wherein the pending transaction request indicator indicates whether the shared memory unit stores a transaction request destined to the ordered bus; and
wherein the updating circuit is arranged to update a dependency resolution attribute of a transaction request that is destined to a relevant ordered bus, based on the last transaction cycle identifier and the pending transaction request indicator associated with the relevant ordered bus.
9. The bus bridge according to claim 1 , wherein the updating circuit is arranged to update a value of the last transaction cycle identifier and to update the pending transaction request indicator upon a dequeueing of a ready transaction request from the shared memory.
10. The bus bridge according to claim 1 , wherein each entry of the shared memory is arranged to store a valid indicator indicative of a validity of the entry, a pending transaction request, an antecedent dependency attribute indicative of an antecedent pending transaction, a dependency resolution attribute and a data readiness attribute.
11. A method for interfacing an out-of-order bus and multiple ordered buses, comprising:
receiving transaction requests from the out-of-order bus;
controlling a flow of transaction requests between the out-of-order bus and each of the ordered buses interfaces; and
performing transactions between the out-of-order bus and the ordered buses based on the flow of transaction requests;
wherein controlling of the flow of transaction requests comprises:
updating dependency resolution attributes and data readiness attributes associated with transaction requests;
storing transaction requests, dependency resolution attributes and data readiness attributes;
determining a readiness of each transaction request based on a dependency resolution attribute and a data readiness attribute associated with the transaction request; and
managing a dequeueing of ready transaction requests to the ordered bus interfaces based on an availability of the ordered bus interfaces.
12. The method according to claim 11 , further comprising arbitrating between ready transaction requests that are associated with different ordered buses.
13. The method according to claim 11 , wherein the transaction requests, dependency resolution attributes and data readiness attributes are stored in a shared memory unit, and wherein the method further comprises:
monitoring a level of fullness of the shared memory unit; and
sending, to an out-of-order bus controller, an availability indicator that is indicative of an ability of the shared memory to receive transaction requests.
14. The method according to claim 13 , further comprising:
receiving a data readiness indicator that is indicative of an availability of data that corresponds to a relevant transaction cycle and is destined to a relevant ordered bus;
searching the shared memory unit for a matching write transaction request; and
updating the data readiness attribute associated with the matching write transaction request.
15. The method according to claim 11 , further comprising updating the data readiness attribute of a read transaction request to indicate that the data of the read transaction request is ready.
16. The method according to claim 11 , further comprising: controlling a flow of transaction request responses from the ordered bus interfaces to the out-of-order bus, wherein the controlling comprises arbitrating between transaction request responses that originate from different ordered bus interfaces.
17. The method according to claim 11 , further comprising:
storing in a shared memory unit a maximal number of pending transaction requests and storing in each ordered bus interface a maximal number of ready transaction requests;
wherein the maximal number of pending transaction requests is greater than the maximal number of ready transaction requests.
18. The method according to claim 11 , further comprising:
storing in a shared memory unit, for each ordered bus, a last transaction cycle identifier and a pending transaction request indicator; and
updating a dependency resolution attribute of a transaction request that is destined to a relevant ordered bus, based on the last transaction cycle identifier and the pending transaction request indicator associated with the relevant ordered bus.
19. The method according to claim 18 , further comprising:
updating a value of the last transaction cycle identifier; and
updating the pending transaction request indicator upon a dequeueing of an associated ready transaction request from the shared memory.
20. The method according to claim 19 , further comprising storing in each entry of the shared memory unit a valid indicator indicative of a validity of the entry, a pending transaction request, an antecedent dependency attribute indicative of an antecedent pending transaction, a dependency resolution attribute and a data readiness attribute.