SOI SiGe-base lateral bipolar junction transistor
View Patent ↗A lateral heterojunction bipolar transistor (HBT) is formed on a semiconductor-on-insulator substrate. The HBT includes a base including a doped silicon-germanium alloy base region, an emitter including doped silicon and laterally contacting the base, and a collector including doped silicon and laterally contacting the base. Because the collector current is channeled through the doped silicon-germanium base region, the HBT can accommodate a greater current density than a comparable bipolar transistor employing a silicon channel. The base may also include an upper silicon base region and/or a lower silicon base region. In this case, the collector current is concentrated in the doped silicon-germanium base region, thereby minimizing noise introduced to carrier scattering at the periphery of the base. Further, parasitic capacitance is minimized because the emitter-base junction area is the same as the collector-base junction area.
1. A semiconductor structure comprising:
a base including at least a silicon-germanium alloy base region having a doping of a first conductivity type;
an emitter including a first doped silicon region having a doping of a second conductivity type that is the opposite of said first conductivity type, wherein a first lateral heterojunction is present at a first interface between said first doped silicon region and said silicon-germanium alloy region;
a collector including a second doped silicon region having a doping of said second conductivity type, wherein a second lateral heterojunction is present at a second interface between said second doped silicon region and said silicon-germanium alloy region; and
an extrinsic base contacting a top surface of said base and including a semiconductor material having a doping of said first conductivity type.
2. The semiconductor structure of claim 1 , wherein said base, said emitter, and said collector contact a top surface of a buried insulator layer of a semiconductor-on-insulator (SOI) substrate.
3. The semiconductor structure of claim 1 , further comprising a dielectric spacer laterally surrounding said extrinsic base, wherein a first portion of a bottom surface of said dielectric spacer contacts an upper end of said first lateral heterojunction, and a second portion of said bottom surface of said dielectric spacer contacts an upper end of said second lateral heterojunction.
4. The semiconductor structure of claim 3 , wherein an entirety of an interface between said base and said extrinsic base is located in a single horizontal plane.
5. The semiconductor structure of claim 4 , wherein an entirety of said bottom surface of said dielectric spacer is located in said single horizontal plane.
6. The semiconductor structure of claim 1 , wherein a protruding portion of said emitter and a protruding portion of said collector are present above a plane of an interface between said base and said extrinsic base.
7. The semiconductor structure of claim 6 , wherein a first plurality of crystallographic facets having different crystallographic orientations is present on said protruding portion of said emitter, and a second plurality of crystallographic facets having different crystallographic orientations is present on said protruding portion of said collector.
8. The semiconductor structure of claim 1 , further comprising a shallow trench isolation structure laterally surrounding and contacting said emitter, said base, and said collector.
9. The semiconductor structure of claim 1 , wherein an entirety of said base is single crystalline, and said extrinsic base is polycrystalline.
10. The semiconductor structure of claim 1 , wherein said base further includes a lower silicon base region having a doping of said first conductivity type, contacting a bottom surface of said silicon-germanium alloy base region, said emitter, said collector, and a buried insulator layer of a semiconductor-on-insulator substrate.
11. The semiconductor structure of claim 1 , wherein said base further includes an upper silicon base region having a doping of said first conductivity type, contacting a top surface of said silicon-germanium alloy base region, said emitter, said collector, and a bottom surface of said extrinsic base.
12. The semiconductor structure of claim 1 , wherein said base further includes:
a lower silicon base region having a doping of said first conductivity type and contacting a bottom surface of said silicon-germanium alloy base region, said emitter, said collector, and a buried insulator layer of a semiconductor-on-insulator substrate; and
an upper silicon base region having a doping of said first conductivity type and contacting a top surface of said silicon-germanium alloy base region, said emitter, said collector, and a bottom surface of said extrinsic base.
13. The semiconductor structure of claim 1 , wherein said base consists of said silicon-germanium alloy base region.