Flash memory device and operating method of flash memory device
Disclosed is an operating method of a flash memory device, which includes normal memory cells and dummy memory cells. The operating method includes programming the normal memory cells and programming the dummy memory cells. A dummy pass voltage used for programming the dummy memory cells is different from a normal pass voltage used for programming the normal memory cells.
1. An operating method of a flash memory device comprising normal memory cells and dummy memory cells, the normal memory cells are connected in series, and the dummy memory cells are connected to each end of the series connected normal memory cells forming a string of memory cells, the operating method comprising: programming the normal memory cells of the string by applying a first program voltage to a selected normal word line to program a selected normal memory cell; and programming the dummy memory cells by applying a second program voltage to a selected dummy word line to program a selected dummy memory cell, the second program voltage being different from the first program voltage, wherein a dummy pass voltage is applied to all unselected normal and dummy word lines of the string during the programming of the dummy memory cells, and a normal pass voltage is applied to all unselected normal and dummy word lines of the string during the programming of the normal memory cells, the dummy pass voltage being lower than the normal pass voltage.
2. The operating method of claim 1 , wherein the dummy memory cells are programmed to have threshold voltages higher than a ground voltage.
3. The operating method of claim 2 , wherein the dummy memory cells have a programmed state after programming the dummy memory cells.
4. The operating method of claim 1 , further comprising:
performing an erase operation of the normal memory cells and the dummy memory cells.
5. The operating method of claim 4 , wherein the erase operation is performed after programming the normal memory cells and before programming the dummy memory cells.
6. The operating method of claim 4 , wherein the erase operation is performed after programming the dummy memory cells.
7. The operating method of claim 6 , wherein programming the dummy memory cells is performed after programming the normal memory cells.
8. The operating method of claim 7 , wherein the normal memory cells have a programmed state after programming of the normal memory cells.
9. The operating method of claim 6 , wherein the dummy memory cells have a programmed state after programming the dummy memory cells.
10. The operating method of claim 6 , wherein during the erase operation, the dummy memory cells are not erased, and the normal memory cells are erased.
11. A flash memory device comprising: a memory cell array comprising a plurality of normal memory cells and a plurality of dummy memory cells, the normal memory cells are connected in series, and the dummy memory cells are connected to each end of the series connected normal memory cells forming a string of memory cells; and a controller configured to control program operations and an erase operation with respect to the memory cell array, wherein a second program voltage and a dummy pass voltage used in a program operation of the dummy memory cells is different from a first program voltage and a normal pass voltage, respectively, used in a program operation of the normal memory cell, wherein the dummy pass voltage, which is applied to all unselected dummy and normal memory cells of the string during the program operation of the dummy memory cells is lower than the normal pass voltage, which is applied to all unselected dummy and normal memory cells of the string during the program operation of the normal memory cells.
12. The flash memory device of claim 11 , wherein the controller controls the program operation of the dummy memory cell so that the dummy memory cells are programmed to have threshold voltages higher than a ground voltage.
13. The flash memory device of claim 11 , wherein the controller controls the erase operation and the program operation of the dummy memory cells so that the dummy memory cells are programmed after the erase operation.
14. The flash memory device of claim 11 , wherein the controller controls the program operation of the dummy memory cells so that the dummy memory cells are programmed before the erase operation.
15. The flash memory device of claim 14 , wherein the controller controls the program operation of the normal memory cells so that the normal memory cells are all programmed before the program operation of the dummy memory cells.
16. The flash memory device of claim 14 , wherein the controller controls the program operation of the dummy memory cells such that the dummy memory cells have threshold voltages higher than a power supply voltage.
17. The flash memory device of claim 14 , wherein the controller controls the erase operation such that the normal memory cells are erased and the dummy memory cells are not erased.