Technique for linearizing the voltage-to-frequency response of a VCO
View Patent ↗Apparatuses and methods are provided relating to a voltage controlled oscillator (VCO) based on current starved inverting delay stages; wherein in each stage a PMOS transistor as header and an NMOS transistor as footer are used with their gate-to-source voltages always equal to analog control voltage. The analog control voltage is also used as the supply voltage of the oscillator. An exemplary apparatus includes a VCO of n stages, where n is an odd number and where each stage includes a current starved inverter where the analog control voltage is also used as the supply voltage of each delay stage.
1. A voltage controlled oscillator, comprising:
a plurality of current starved inverter stages, wherein a dedicated NMOS transistor as footer and a dedicated PMOS transistor as header is used for each delay stage, wherein the footer and the header both have a gate-to-source voltage that is equal to an input control voltage, and the input control voltage is also used as a supply voltage of the voltage controlled oscillator, wherein the input control voltage is connected to a source of the header and to a gate of the footer for each delay stage.
2. The voltage controlled oscillator of claim 1 , wherein an oscillation frequency of the voltage controlled oscillator is controlled as a linear function of the input control voltage.
3. The voltage controlled oscillator of claim 1 , wherein the footer and the header are used as respective pull-down and pull-up paths, wherein an on resistance of the pull-up and pull-down paths is modulated with the input control voltage.
4. The voltage controlled oscillator of claim 3 , wherein the on resistance of the pull up/down path is written as in the following equation to the first order:
R
=
β
1
+
β
2
β
1
β
2
(
V
A
-
V
TH
)
wherein V A is the input control voltage, V TH is a threshold voltage, and βi is μC ox (W/L) of an ith transistor, where the ith transistor is one of the NMOS and PMOS transistors, μ is free electron mobility in a channel of the transistor, C ox is the gate oxide capacitance per unit area for the transistor, and W/L is the ratio of the width and length of the channel for the transistor.
5. The voltage controlled oscillator of claim 1 , wherein each of the plurality of current starved inverter stages is a delay stage of the voltage controlled oscillator and comprises four transistors including the header and the footer.
6. The voltage controlled oscillator of claim 1 , comprising an odd number n of the plurality of current starved inverter stages, wherein n is at least 3.
7. The voltage controlled oscillator of claim 1 , wherein the input control voltage is an analog control voltage.
8. The voltage controlled oscillator of claim 1 , wherein the voltage controlled oscillator forms part of a time-to-digital conversion (TDC) based analog-to-digital conversion (ADC) architecture.
9. The voltage controlled oscillator of claim 1 , wherein the voltage controlled oscillator forms part of a multi-processor platform for dynamically adjusting voltage and operation frequency.
10. The voltage controlled oscillator of claim 1 , wherein the voltage controlled oscillator forms part of a phase-locked-loop circuit.
11. A method for linearizing the voltage-to-frequency response of a voltage controlled oscillator, comprising:
assigning an NMOS transistor as footer and a PMOS transistor as header of a current starved inverter stage of the voltage controlled oscillator with the same gate-to-source voltage that is controlled by an input control voltage; and
using the input control voltage as a supply voltage of the voltage controlled oscillator, wherein the input control voltage is connected to a source of the header and to a gate of the footer.
12. The method of claim 11 , further comprising controlling an oscillation frequency of the voltage controlled oscillator as a linear function of the input control voltage.
13. The method of claim 11 , further comprising modulating a resistance of pull-up and pull-down paths of the current starved inverter stage with the input control voltage to linearize a transfer function of the voltage controlled oscillator.
14. The method of claim 11 , further comprising:
using the footer and the header having the gate-to-source voltages equal to each other and also equal to the input control voltage in the respective pull-down and pull-up paths of the current starved inverter stage; and
modulating an on resistance of the pull-up and pull-down paths with the input control voltage.
15. The method of claim 14 , wherein the on resistance of the pull up/down path is written as in the following equation to the first order:
R
=
β
1
+
β
2
β
1
β
2
(
V
A
-
V
TH
)
wherein V A is the input control voltage, V TH is a threshold voltage, and βi is μC ox (W/L) of an ith transistor, where the ith transistor is one of the NMOS and PMOS transistors, μ is free electron mobility in a channel of the transistor, C ox is the gate oxide capacitance per unit area for the transistor, and W/L is the ratio of the width and length of the channel for the transistor.
16. The method of claim 11 , wherein a delay stage is implemented/realized as a current starved inverter.
17. The method of claim 11 , wherein the input control voltage is an analog control voltage.