Comparator receiving expected and mask data from circuit pads
Test circuits located on semiconductor die enable a tester to test a plurality of die/ICs in parallel by inputting both stimulus and response patterns to the plurality of die/ICs. The response patterns from the tester are input to the test circuits along with the output response of the die/IC to be compared. Also disclosed is the use of a response signal encoding scheme whereby the tester transmits response test commands to the test circuits, using a single signal per test circuit, to perform: (1) a compare die/IC output against an expected logic high, (2) a compare die/IC output against an expected logic low, and (3) a mask compare operation. The use of the signal encoding scheme allows functional testing of die and ICs since all response test commands (i.e. 1-3 above) required at each die/IC output can be transmitted to each die/IC output using only a single tester signal connection per die/IC output. In addition to functional testing, scan testing of die and ICs is also possible.
1. A compare circuit comprising:
A. an Exclusive-Or gate having one input connected to a core output, another input connected to an expected data input, and an output;
B. an AND gate having one input connected to the output of the Exclusive-Or gate, another input connected to a mask data input, and a compare output;
C. a pass/fail scan memory having a compare input connected with the compare output, a scan input, a scan control input, and a scan output; and
D. a first circuit pad directly connected with the another input of the Exclusive-Or gate and a second circuit pad directly connected with the another input of the AND gate.
2. The compare circuit of claim 1 in which the pass/fail scan memory includes a compare strobe input.
3. The compare circuit of claim 1 including a test enable lead connected to inputs of the pass/fail scan memory, the AND gate, and the Exclusive-Or gate.