IP Library › Granted Patent US 8,306,125
Granted Patent B2
US 8,306,125 · App. 11/755,698 · Granted Nov 6, 2012

2-bin parallel decoder for advanced video processing

Assignees: Digital Video Systems, Inc.; Mstar Semiconductor, Inc.
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Quick Facts
Patent No.
US 8,306,125
App. No.
11/755,698
Granted
Nov 6, 2012
Kind
B2
Abstract

A critical phase of video processing is the decoding of bit streams coming from standard based heavy compressed sources. Entropy coding can be effectively decoded by adopting parallelism to speed up the process. Reasonable assumptions make possible for example the multiple bits at a time processing for the Context-based Adaptive Binary Arithmetic Coding (CABAC) algorithm. In particular, a clever arithmetic section reduces single propagation for the timing critical path while decoding done for only two sequence elements at a time by calculating and maintaining most probable bit values. This in turn making accelerated path using pre-determined probability outcome through parallelism not cost.

Claims (30)

1. A method of decoding a video bit stream using an efficient parallel algorithm, the method comprising:

inputting and initializing from a previous video processing context;

decoding multiple bits at a time of the previous video processing context, wherein the decoding is performed on most probable bit values for all bits except a last bit; and

receiving the decoded multiple bits and providing an output bit stream for further video processing.

2. The method of claim 1 , wherein the video bit stream includes:

video compression techniques to encode using Advanced Video Coding (AVC) Context-based Adaptive Binary Arithmetic Coding (CABAC) algorithm.

3. The method of claim 1 , wherein a next quantized range used to decode a next bit is highly predictable using a current range value and a current probability stare.

4. The method of claim 1 , wherein only two sequence elements needs to be accelerated to speed up significantly the decoding process.

5. The method of claim 1 , wherein the rate of bits produced is never slower than the single bit sequential method and implementation.

6. The method of claim 1 , wherein the initialization and fetching is done for up to 2 bin at a time for AVC CABAC pState and vaIMPS which are pre-calculated and stored in a DRAM or Flash memory.

7. The method of claim 1 , further including:

utilizing an arithmetic section using carry save adders, reducing to single carry propagation for the timing critical adder paths.

8. The method of claim 2 , further comprising:

utilizing an AVC CABAC 2-bin 1-bit slice Arithmetic Evaluator.

9. A system for decoding a video bit stream using an efficient parallel algorithm, the system comprising:

a main memory for inputting and initializing from a previous video processing context;

a decoder for decoding multiple bits of the previous video processing context at a rime, wherein the decoding is performed on most probable bit values for all bits except a last bit; and

a sequencer for receiving the decoded multiple bits and providing an output bit stream for further video processing.

10. The system of claim 9 , wherein the video bit stream includes:

video compression techniques to encode using Advanced Video Coding (AVC) Context-based Adaptive Binary Arithmetic Coding (CABAC) algorithm.

11. The system of claim 9 , wherein the decoder further:

decodes Most Probable bit values for all bits except a last bit decoded.

12. The system of claim 9 , wherein a next quantized range used to decode the next bit is highly predictable using a current range value and a current probability state.

13. The system of claim 9 , wherein only two sequence elements needs to be accelerated to speed up significantly the decoding process.

14. The system of claim 9 , wherein output bit stream bit rate of bits produced is never slower than a single bit sequential method and implementation.

15. The system of claim 9 , wherein the inputting and initialization is performed for up to 2 bin at a time for AVC CABAC pState and vaIMPS which are pre-calculated and stored in a DRAM or Flash memory.

16. The system of claim 9 , further including:

an arithmetic section using save carry save adders, reducing to single carry propagation for timing critical adder paths.

17. The system of claim 9 , further comprising:

an AVC CABAC 2-bin 10-bit slice Arithmetic Evaluator.

Assignments (6)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Aug 10, 2015
From: MSTAR SEMICONDUCTOR, INC.
To: DIGITAL VIDEO SYSTEMS INC.
Reel/Frame 036289/0346 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jun 24, 2010
From: MEGAPOWER INTELLECTUAL PROPERTY USA HOLDING CORPORATION
To: MIRFAK INVESTMENT LIMITED
Reel/Frame 024587/0153 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jun 24, 2010
From: MIRFAK INVESTMENT LIMITED
To: MSTAR SEMICONDUCTOR, INC.
Reel/Frame 024587/0256 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded May 13, 2010
From: MIRFAK INVESTMENT LIMITED
To: MEGAPOWER INTELLECTUAL PROPERTY USA HOLDING CORPORATION
Reel/Frame 024382/0665 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Apr 13, 2010
From: DIGITAL VIDEO SYSTEMS INC.
To: DIGITAL VIDEO SYSTEMS INC.; MIRFAK INVESTMENT LIMITED
Reel/Frame 024227/0357 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Feb 11, 2010
From: KAO, I-PIENG PETER; BENKUAL, JACK
To: DIGITAL VIDEO SYSTEMS, INC. (DVS)
Reel/Frame 023926/0602 →
Continuity (2)
Provisional Application 60815749 · Jun 21, 2006
Related Publication 20090196355A1 · Aug 6, 2009