Transistor structures and methods of fabrication thereof

1. An electronic device comprising active elements comprising a source electrode, a drain electrode, and a channel, wherein the source and drain electrodes are located in separate regions in a same layer, the channel is located in a region between the source and drain electrodes, and is associated with a patterned electrically-conductive layer, which has a pattern defining an array of spaced-apart regions of different electrical conductivity, forming discontinuity of electrical conductivity along said channel thereby increasing an electric current through the channel.

2. The device of claim 1 , comprising a thin film transistor structure.

3. The device of claim 2 , wherein said thin film transistor has a channel made of a semiconductor material.

4. The device of claim 2 , wherein said thin film transistor has a channel made of a polymer material.

5. The device of claim 4 , comprising a block copolymer layer serving as a substrate for said patterned electrically conductive layer.

6. The device of claim 5 , wherein said block copolymer layer serves as a template for said pattern in the electrically conductive layer.

7. The device of claim 2 , wherein said thin film transistor has a channel made of a polysilicon.

8. The device of claim 2 , wherein the channel of said thin film transistor is made of amorphous silicon.

9. The device of claim 8 , wherein said transistor structure comprises a gate electrode covered by an electrical insulator, the amorphous silicon channel layer on top of said electrical insulator, and a layer containing said source and drain electrodes above the channel with regions of n+ amorphous silicon in between the channel and the source and drain electrodes, said layer containing said source and drain electrodes being said patterned electrically conductive layer defining the array of spaced-apart electrically conductive regions within a region above the channel in between the source and drain electrodes.

10. The device of claim 9 , wherein each of said spaced-apart electrically conductive regions is a stack formed by n+ amorphous silicon and metal on top thereof.

11. The device of claim 8 , wherein said transistor structure comprises a gate electrode covered by an electrical insulator, the array of spaced-apart electrically conductive regions of said patterned electrically conductive layer on top of said electrical insulator, the amorphous silicon channel layer on top of said patterned electrically conductive layer, and source and drain electrodes above the channel with regions of n+ amorphous silicon in between the channel and the source and drain electrodes.

12. The device of claim 11 , wherein said patterned electrically conductive layer is made of n+ amorphous silicon.

13. The device of claim 8 , wherein said transistor structure comprises a gate electrode covered by a first electrical insulator, the amorphous silicon channel layer on top of said electrical insulator, a second electrical insulator layer on top of said channel layer, and a layer containing said source and drain electrodes above said second insulator such that the source and drain electrode have electrical contact to the channel, said layer containing said source and drain electrodes being said patterned electrically conductive layer defining the array of spaced-apart electrically conductive regions within a region above the channel in between the source and drain electrodes.

14. The device of claim 2 , wherein said transistor device comprises a gate electrode, the channel with its associated patterned electrically conductive layer being located above said gate electrode and electrically insulated therefrom, and a layer containing said source and drain electrodes being located above the channel and having electrical contact thereto.

15. The device of claim 14 , comprising an electrically conductive region serving as a second floating gate electrode located between and electrically insulated from the source and drain electrodes and from said channel element.

16. The device of claim 14 , wherein said source and drain electrodes have extended regions thereof extending above corresponding regions of the channel element and electrically insulated therefrom.

17. The device of claim 14 , wherein each of said spaced-apart electrically conductive regions is formed by n+ amorphous silicon.

18. The device of claim 14 , wherein each of said spaced-apart electrically conductive regions is formed by metal.

19. The device of claim 2 , wherein said transistor structure is configured and operable as a thin film transistor structure with source and drain electrodes arranged in different layers, said patterned electrically-conductive layer being either one of the source and drain electrodes.

20. The device of claim 19 , wherein said patterned electrode is the source electrode located above a gate electrode, the source electrode metal being selected to operate as a barrier to charge injection into a semiconductor layer between the source and drain electrodes.

21. The device of claim 19 , wherein said patterned electrode is the drain electrode located above a gate electrode, the source electrode metal being selected to operate as a barrier to charge injection into a semiconductor layer between the source and drain electrodes.

22. The device of claim 21 , wherein said transistor structure comprises an additional layer structure between the source electrode layer and a channel element, said additional layer structure being configured to optimize the charge injection properties and/or enhance the chemical compatibility of the source and channel elements.

23. The device of claim 22 , wherein said additional layer structure is a dielectric structure.

24. The device of claim 21 , wherein said transistor structure comprises a dielectric structure placed between a channel element and the source electrode.

25. The device of claim 19 , wherein the patterned electrode is a perforated metal layer.

26. The device of claim 19 , wherein said transistor structure comprises a block copolymer configured to operate as an insulator material and as template for the patterned source or drain electrode.

27. The device of claim 26 , wherein the transistor structure comprises a gate electrode, a gate dielectric structure on top of the gate electrode, a patterned layer of the source electrode on top of the gate dielectric structure and carrying a semiconductor channel element, and the top drain electrode, said gate dielectric structure including the dielectric and the block polymer thin film.

28. The device of claim 27 , wherein the patterned source electrode is a perforated metal layer with perforations of a characteristic diameter comparable to the thickness of the semiconductor layer.

29. The device of claim 27 , wherein said transistor structure is Si-based structure with Ag-electrodes.

30. The device of claim 27 , wherein the source electrode is porous metal layer produced by nanoscale patterning of surface energy.

31. The device of claim 30 , wherein the source electrode is configured as a network of metal stripes.

32. The device of claim 26 , wherein the transistor structure comprises a gate electrode, a gate dielectric structure on top of the gate electrode, a patterned layer of the drain electrode on top of the gate dielectric structure and carrying a semiconductor channel element, and the top source electrode, said gate dielectric structure including the dielectric and the block polymer thin film.

33. The device of claim 1 , wherein said electrically conductive layer is in the form of an array of islands of the electrically conductive material arranged in spaced-apart relationship along the region between the source and drain electrodes above said channel.

34. The device of claim 33 , wherein said array extends along at least one axis inclined with respect to an axis of the channel.

35. The device of claim 1 , wherein said electrically conductive layer is in the form of an array of islands of the electrically conductive material arranged in spaced-apart relationship along the region between the source and drain electrodes below said channel.

36. The device of claim 1 , wherein said electrically conductive layer is in the form of an array of elongated regions of the electrically conductive material arranged in spaced-apart relationship along the region between the source and drain electrodes above said channel.

37. The device of claim 1 , wherein said electrically conductive layer is in the form of the array of elongated regions of the electrically conductive material arranged in spaced-apart relationship in the region along the channel element below said channel element.

38. The device of claim 1 , wherein said pattern is in the form of a two-dimensional array of the regions of different electrical conductivity.

39. A lateral configuration thin film transistor device comprising source and drain electrodes located in separate regions of a same layer, and a channel element located in a region between the source and drain electrodes, said channel element having a pattern forming discontinuity of electrical conductivity along the channel, the pattern comprising a two-dimensional array of spaced-apart regions of a material of higher electrical conductivity spaced by regions of lower electrical conductivity.

40. The device of claim 39 , wherein said channel element comprises a layer of the first, lower electrical conductivity material selectively doped with a second material of the higher electrical conductivity within said spaced-apart regions arranged in the two-dimensional array.

41. The device of claim 39 , wherein said channel element comprises a first continuous layer of the lower electrical conductivity material, and a second layer located close to said first layer and being patterned to define said two dimensional array of the regions of the higher electrical conductivity material.

42. The device of claim 41 , wherein said second patterned layer is located between the first layer and the source and drain containing layer.

43. The device of claim 42 , comprising an insulating layer between the first layer and the patterned second layer.

44. The device of claim 41 , wherein said second patterned layer is located below the first layer, on top of a gate insulator layer.