Method of fabricating a FinFET device

1. A FinFET device comprising:

a substrate of a crystalline semiconductor material having a top surface of a first crystal plane orientation;

a fin structure of the crystalline semiconductor material overlying the substrate;

a gate structure over a first portion of the fin structure;

an epitaxy layer over a second portion of the fin structure, wherein the epitaxy layer includes:

a top surface of the epitaxy layer parallel with the top surface of the substrate; and

a first surface and a second surface disposed as sidewall surfaces that are perpendicular to the top surface of the epitaxy layer; and wherein the first surface has a second crystal plane orientation, the second crystal plane orientation different than the first crystal plane orientation;

wherein the epitaxy layer and underlying fin structure include a source and drain region, the source region being separated from the drain region by the gate structure; and

a channel defined in the fin structure from the source region to the drain region, and aligned in a direction parallel to both the first surface of the epitaxy layer and the top surface of the substrate.

2. The FinFET device of claim 1 wherein the first crystal plane orientation is a (001) crystal plane orientation and the second crystal plane orientation is a (110) crystal plane orientation.

3. The FinFET device of claim 2 wherein the channel being parallel with the first surface of the epitaxy layer is aligned in the <110> direction.

4. The FinFET device of claim 1 wherein the epitaxy layer includes at least one of silicon or silicon germanium.

5. The FinFET device of claim 1 wherein the epitaxy layer includes silicon doped with a phosphorous doping species.

6. The FinFET device of claim 1 wherein the top surface of the epitaxial layer has the first crystal plane orientation and the two sidewall surfaces have the second crystal plane orientation.

7. The FinFET device of claim 1 wherein the crystalline semiconductor material is silicon.

8. The FinFET device of claim 1 wherein the epitaxy layer is formed by performing a damascene process that includes:

forming a capping layer over the substrate, the fin structure, and the gate structure;

patterning the capping layer to form an opening, wherein the opening exposes the second portion of the fin structure;

growing the epitaxy layer in the opening on the exposed second portion of the fin structure; and

removing the capping layer.

9. The FinFET device of claim 1 wherein the epitaxy layer is formed by performing a damascene process that includes:

removing a third portion of the fin structure overlying the second portion of the fin structure, to form a recessed portion of the fin structure;

forming a capping layer over the substrate, fin structure, and gate structure;

patterning the capping layer to form an opening, wherein the opening exposes the recessed portion of the fin structure;

growing the epitaxy layer in the opening on the exposed recessed portion of the fin structure; and

removing the capping layer.

10. The FinFET device of claim 9 wherein the damascene process further includes performing an implantation process.

11. The FinFET device of claim 1 wherein the gate structure directly contacts the fin structure, and the gate structure includes a gate dielectric layer and a gate conductive layer on the gate dielectric layer.

12. A FinFET device comprising:

a substrate including a fin structure, wherein the substrate is crystalline silicon and has a top surface with a first crystallographic plane orientation;

a gate structure disposed on a portion of the fin structure, the gate structure traversing the fin structure;

an epitaxy layer formed over another portion of the fin structure, wherein the epitaxy layer has first, second, and third surfaces, the first surface being parallel to the top surface of the substrate and the second and third surfaces being perpendicular to the first surface, and wherein the second and third surfaces each have a second crystallographic plane orientation different than the first crystallographic plane orientation; and

a source region and drain region in the epitaxy layer that defines a channel in the fin structure from the source region to the drain region, the channel being aligned in a direction defined by an intersection line between the first surface and the second surface.

13. The FinFET device of claim 12 wherein the fin structure and the epitaxy layer have a rectangular profile in a sectional view along the channel.

14. The FinFET device of claim 12 wherein the first crystallographic plane orientation is a (001) crystal plane orientation, and the second crystallographic plane orientation is a (110) crystal plane orientation.

15. The FinFET device of claim 12 wherein the channel being aligned in the direction includes the channel being aligned in a <110> direction.

16. The FinFET device of claim 12 wherein the epitaxy layer comprises at least one of silicon and silicon germanium.

17. A FinFET device comprising:

a semiconductor substrate having a fin structure disposed thereover, the fin structure having a top surface parallel to a top surface of the semiconductor substrate, the top surfaces having a (001) crystal plane orientation;

a gate structure traversing the fin structure, the gate structure separating a source region and a drain region of the fin structure, wherein the source region and the drain region define a channel therebetween and are aligned in a <110> direction; and

the source region and the drain region including an epitaxial layer having a top surface and two sidewall surfaces, wherein the top surface has a (001) crystal plane orientation, and the two sidewall surfaces can have a (110) crystal plane orientation.

18. The FinFET device of claim 17 wherein the epitaxy layer includes at least one of silicon and silicon germanium.

19. The FinFET device of claim 17 wherein the semiconductor substrate and the fin structure include silicon.