Method and structure for provably fair random number generator

1. A random number generator, comprising:

an output terminal;

a random number generating module that generates a sequence of random numbers as an output to be selectively provided to said output terminal; and

a fairness checker and correction module that ensures that a complete random sequence will be output by said random number generator within a predetermined bounded time, said complete random sequence comprising a condition that each number possible to be generated by said random number generator occurs at least one time in said complete random sequence,

wherein said random number generating module and said fairness checker and correction module are tangibly embodied in a program of machine-readable instructions executable by a digital processing apparatus on a non-transitory, computer-readable storage medium.

2. The random number generator of claim 1 , wherein said fairness checker and correction module monitors said sequence of random numbers for numbers missing from said complete random sequence in a window of time related to said predetermined bounded time.

3. The random number generator of claim 2 , further comprising:

a multiplexer function controlled by said fairness checker and correction module, an output of said multiplexer providing numbers to be applied to said output terminal, a first input of said multiplexer receiving said sequence of random numbers from said random number generator and a second input of said multiplexer receiving said missing numbers from said fairness checker and correction module, said fairness checker and correction module controlling when said missing numbers are inserted into said output of said random number generator.

4. The random number generator of claim 2 , wherein said missing numbers are determined by monitoring which numbers of said complete random sequence have not yet occurred within said window of time of said random number generator.

5. The random number generator of claim 1 , further comprising:

a counter that counts clock cycles and compares a number of said clock cycles with said predetermined bounded time.

6. The random number generator of claim 1 , wherein said predetermined bounded time is adjustable by a user input.

7. The random number generator of claim 1 , wherein said computer-readable storage medium comprises one of:

a stand-alone diskette to be inserted into a computer disk drive;

a read-only memory (ROM) on a computer storing said machine-readable instructions as ready to be executed by said computer or to be transmitted to another computer; and

a random-access memory (RAM) on said computer as currently executing said machine-readable instructions.

8. A fairness checker and correction module for a random number generator, comprising:

logic, as tangibly embodied in a program of machine-readable instructions executable by a digital processing apparatus on a non-transitory, computer-readable storage medium, that ensures that a complete random sequence will be output within a predetermined bounded time, said complete random sequence comprising a condition that each number possible to be generated by said random number generator occurs at least one time in said complete random sequence.

9. The fairness checker and correction module of claim 8 , further comprising:

an input receiving a sequence of random numbers generated by a random number generator, said input sequence of random numbers being checked by said logic, to ensure said complete random sequence; and

a monitor monitoring said input sequence of random numbers for numbers missing from said complete random sequence in a window of time related to said predetermined bounded time.

10. The fairness checker and correction module of claim 9 , further comprising:

a controller for a multiplexer, an output of said multiplexer providing numbers to be the output of said random number generator, a first input of said multiplexer receiving said sequence of random numbers from said random number generator and a second input of said multiplexer receiving said missing numbers from said fairness checker and correction module, said fairness checker and correction module controlling when said missing numbers are inserted into said output of said random number generator.

11. The fairness checker and correction module of claim 8 , further comprising:

a counter that counts clock cycles and compares a number of said clock cycles with said predetermined bounded time, wherein said missing numbers are determined by monitoring which numbers of said complete random sequence have not yet occurred within said window of time of said random number generator.

12. The fairness checker and correction module of claim 8 , wherein said predetermined bounded time is adjustable by a user input.