Indirect function call instructions in a synchronous parallel thread processor
An indirect branch instruction takes an address register as an argument in order to provide indirect function call capability for single-instruction multiple-thread (SIMT) processor architectures. The indirect branch instruction is used to implement indirect function calls, virtual function calls, and switch statements to improve processing performance compared with using sequential chains of tests and branches.
1. A method for executing indirect function calls in a synchronous parallel thread processor, the method comprising:
receiving a first control instruction that references a set of pointers to one or more functions, the pointers specifying addresses of the one or more functions;
determining that two of the pointers corresponding to different active threads in a thread group differ from one another, thereby indicating that the active threads are to diverge and are to execute different functions included in the one or more functions in the synchronous parallel thread processor;
in response, pushing a first token onto an execution stack, the first token including an address of the first control instruction, a token type, and a mask that indicates each thread in the thread group that is active and is to execute a function included in the one or more functions that is different than a first function included in the one or more functions; and
updating an active program counter to specify an address of a first function included in the one or more functions;
modifying an active mask to disable the processing of any thread in the thread group that is execute a function included in the one or more functions that is different than the first function; and
executing the first function.
2. The method of claim 1 , further comprising:
receiving, prior to the first control instruction, a second control instruction that specifies a target address of an instruction to be executed after the first function are executed;
pushing a second token onto the execution stack prior to the pushing of the first token; and
updating an active program counter to specify an instruction in the program that is immediately subsequent to the second control instruction.
3. The method of claim 2 , wherein the second token includes a token type, the target address, and a mask indicating the active threads in the thread group that should be processed in parallel when the second token is popped from the execution stack and execution of the program continues at the target address.
4. The method of claim 1 , further comprising:
receiving a second control instruction in the program;
determining that the second control instruction is a return instruction;
popping the first token from the execution stack;
setting the active mask to the mask included in the first token; and
setting the active program counter to the address of the first control instruction included in the first token.
5. The method of claim 1 , wherein, for each unique pointer in the set of pointers that corresponds to at least one active thread in the thread group, the first control instruction is executed once to execute one of the one or more functions for the at least one active thread.
6. The method of claim 1 , wherein an operand associated with the first control instruction specifies a register for each thread of the thread group that stores indices corresponding to one or more entries in a table that lists the set of pointers.
7. The method of claim 1 , wherein an operand associated with the first control instruction specifies a register for each thread of the thread group that stores the set of pointers.
8. The method of claim 1 , wherein a pointer in the set of pointers is computed when executing the program.
9. A non-transitory computer readable medium storing instructions for causing a synchronous parallel processor to execute indirect function calls by performing the steps of:
receiving a first control instruction that references a set of pointers to one or more functions, the pointers specifying addresses of the one or more functions;
determining that two of the pointers corresponding to different active threads in a thread group differ from one another, thereby indicating that the active threads are to diverge and are to execute different functions included in the one or more functions in the synchronous parallel thread processor;
in response, pushing a first token onto an execution stack, the first token including an address of the first control instruction, a token type, and a mask that indicates each thread in the thread group that is active and is to execute a function included in the one or more functions that is different than a first function included in the one or more functions; and
updating an active program counter to specify an address of a first function included in the one or more functions;
modifying an active mask to disable the processing of any thread in the thread group that is execute a function included in the one or more functions that is different than the first function; and
executing the first function.
10. The computer readable medium of claim 9 , wherein, for each unique pointer in the set of pointers that corresponds to at least one active thread in the thread group, the first control instruction is executed once to execute one of the one or more functions for the at least one active thread.
11. The computer readable medium of claim 9 , wherein an operand associated with the first control instruction specifies a register for each thread of the thread group that stores indices corresponding to one or more entries in a table that lists the set of pointers.
12. The computer readable medium of claim 9 , wherein an operand associated with the first control instruction specifies a register for each thread of the thread group that stores the set of pointers.
13. The computer readable medium of claim 9 , further comprising:
receiving, prior to the first control instruction, a second control instruction that specifies a target address of an instruction to be executed after the first function are executed;
pushing a second token onto the execution stack prior to the pushing of the first token; and
updating an active program counter to specify an instruction in the program that is immediately subsequent to the second control instruction.
14. The computer readable medium of claim 13 , wherein the second token includes a token type, the target address, and a mask indicating the active threads in the thread group that should be processed in parallel when the second token is popped from the execution stack and execution of the program continues at the target address.
15. The computer readable medium of claim 9 , further comprising:
receiving a second control instruction in the program;
determining that the second control instruction is a return instruction;
popping the first token from the execution stack;
setting the active mask to the mask included in the first token; and
setting the active program counter to the address of the first control instruction included in the first token.
16. The computer readable medium of claim 9 , wherein a pointer in the set of pointers is computed when executing the program.