Power management for systems on a chip
View Patent ↗A system for controlling a multitasking microprocessor system includes an interconnect, a plurality of processing units connected to the interconnect forming a single-source, single-sink flow network, wherein the plurality of processing units pass data between one another from the single-source to the single-sink, and a monitor connected to the interconnect for monitoring a portion of a resource consumed by each of the plurality of processing units and for controlling the plurality of processing units according to a predetermined budget for the resource to control a data overflow condition, wherein the monitor controls performance and power modes of the plurality of processing units.
1. A system for controlling a multitasking microprocessor system, comprising:
an interconnect;
a plurality of processing units connected to the interconnect forming a single-source, single-sink flow network, wherein the plurality of processing units pass data between one another from the single-source to the single-sink; and
a monitor connected to the interconnect for monitoring a portion of a resource consumed by each of the plurality of processing units and for controlling the plurality of processing units according to a predetermined budget for the resource to control a data overflow condition, wherein the monitor controls performance and power modes of the plurality of processing units,
wherein the monitor performs an iterative max-flow method.
2. The system of claim 1 , further comprising:
a cache connected to the interconnect for receiving overflow data; and
a memory connected to the cache, wherein the monitor monitors reads and writes to a page of the memory.
3. The system of claim 1 , wherein the monitor performs the iterative max-flow method and improves a performance target given the predetermined budget.
4. The system of claim 3 , wherein the predetermined budget includes one of a power, bandwidth and temperature budget.
5. The system of claim 1 , wherein at least two of the processing units are arranged in series.
6. The system of claim 1 , wherein at least two of the processing units are arranged in parallel.
7. A system for controlling a multitasking microprocessor system, comprising:
an interconnect;
a plurality of processing units connected to the interconnect forming a single-source, single-sink flow network, wherein the plurality of processing units pass data between one another from the single-source to the single-sink; and
a monitor connected to the interconnect for monitoring a portion of a resource consumed by each of the plurality of processing units and for controlling the plurality of processing units according to a predetermined budget for the resource to control a data overflow condition, wherein the monitor controls performance and power modes of the plurality of processing units,
wherein the monitor performs an iterative min-flow method.
8. The system of claim 7 , further comprising:
a cache connected to the interconnect for receiving overflow data; and
a memory connected to the cache, wherein the monitor monitors reads and writes to a page of the memory.
9. The system of claim 7 , wherein the monitor performs the iterative min-flow method and improves a performance target given the predetermined budget.
10. The system of claim 9 , wherein the predetermined budget includes one of a power, bandwidth and temperature budget.
11. The system of claim 7 , wherein at least two of the processing units are arranged in series.
12. The system of claim 7 , wherein at least two of the processing units are arranged in parallel.