IP Library Granted Patent US 8,314,491
Granted Patent B2
US 8,314,491 · App. 12/845,937 · Granted Nov 20, 2012

Manufacturing method of semiconductor device and semiconductor device

Assignee: Kabushiki Kaisha Toshiba
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Quick Facts
Patent No.
US 8,314,491
App. No.
12/845,937
Granted
Nov 20, 2012
Kind
B2
Abstract

According to one embodiment, a manufacturing method of a semiconductor device attained as follows. A dielectric layer having a first opening and a second opening reaching an electrode terminal is formed by modifying a photosensitive resin film on a substrate on which the electrode terminal of a first conductive layer is provided. Next, a second conductive layer that is electrically connected to the electrode terminal is formed on the dielectric layer that includes inside of the first opening, and a third conductive layer that has an oxidation-reduction potential of which difference from the oxidation-reduction potential of the first conductive layer is smaller than a difference of the oxidation-reduction potential between the first conductive layer and the second conductive layer is formed on the second conductive layer. Next, a dielectric layer having a third opening reaching the third conductive layer and a fourth opening reaching the electrode terminal via the second opening is formed by modifying a photosensitive resin film, and a bump that is electrically connected to the third conductive layer is formed.

Claims (11)

1. A semiconductor device comprising:

a semiconductor substrate that is provided with a semiconductor element and an electrode terminal including a first conductive layer for the semiconductor element on a surface;

a first dielectric layer that is formed on a main surface on which the electrode terminal is provided of the semiconductor substrate, has a first opening and a second opening reaching the electrode terminal in an area on the electrode terminal, and is formed by modifying a photosensitive resin;

a redistribution that is provided to fill in at least the first opening and includes a second conductive layer that is electrically connected to the electrode terminal;

a conductive protective layer that is formed on an uppermost layer of the redistribution, and includes a third conductive layer that has an oxidation-reduction potential of which difference from the oxidation-reduction potential of the first conductive layer is smaller than a difference of the oxidation-reduction potential between the first conductive layer and the second conductive layer;

a second dielectric layer that is formed on the first dielectric layer and the conductive protective layer, has a third opening reaching the conductive protective layer and a fourth opening reaching the electrode terminal via the second opening, and is formed by modifying a photosensitive resin; and

a bump that fills in at least the third opening and is formed on the conductive protective layer.

2. The semiconductor device according to claim 1 , wherein the first conductive layer comprises aluminum, the second conductive layer comprises copper, and the third conductive layer comprises at least one metal selected from the group consisting of manganese, tantalum, zinc, chrome, cobalt, nickel, tin, and lead.

3. The semiconductor device according to claim 1 , wherein the conductive protective layer includes a first conductive protective layer including the third conductive layer formed on the redistribution and a second conductive protective layer that includes metal oxide of the third conductive layer more than the first conductive protective layer and is formed on the first conductive protective layer.

4. The semiconductor device according to claim 3 , wherein the first conductive layer comprises aluminum, the second conductive layer comprises copper, and the third conductive layer comprises at least one metal selected from the group consisting of manganese, tantalum, zinc, chrome, cobalt, nickel, tin, and lead.

5. The semiconductor device according to claim 4 , wherein the third conductive layer is nickel and the metal oxide is nickel oxide (II).

Assignments (5)
CHANGE OF NAME AND ADDRESS Recorded Jan 22, 2021
From: K.K. PANGEA
To: TOSHIBA MEMORY CORPORATION
Reel/Frame 055669/0401 →
MERGER Recorded Jan 22, 2021
From: TOSHIBA MEMORY CORPORATION
To: K.K. PANGEA
Reel/Frame 055659/0471 →
CHANGE OF NAME AND ADDRESS Recorded Jan 22, 2021
From: TOSHIBA MEMORY CORPORATION
To: KIOXIA CORPORATION
Reel/Frame 055669/0001 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Aug 24, 2017
From: KABUSHIKI KAISHA TOSHIBA
To: TOSHIBA MEMORY CORPORATION
Reel/Frame 043709/0035 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Sep 30, 2010
From: YAMASHITA, SOICHI; MIGITA, TATSUO; IIJIMA, TADASHI; MIYATA, MASAHIRO; UCHIDA, MASAYUKI; TOGASAKI, TAKASHI; EZAWA, HIROKAZU
To: KABUSHIKI KAISHA TOSHIBA
Reel/Frame 025073/0863 →
Priority Claims (2)
JP 2009-178179 · Jul 30, 2009 · national
JP 2010-143085 · Jun 23, 2010 · national
Continuity (1)
Related Publication 20110024901A1 · Feb 3, 2011