Methods of forming integrated circuit devices including a capacitor

1. A method of forming a capacitor of an integrated circuit device, comprising:

forming a lower electrode of the capacitor on an integrated circuit substrate without exposing a contact plug to be coupled to the lower electrode;

forming a supporting conductor coupling the lower electrode to the contact plug after forming the lower electrode;

forming a capacitor dielectric layer on the lower electrode; and

forming an upper electrode of the capacitor on the capacitor dielectric layer,

wherein forming the capacitor dielectric layer is preceded by forming an additional lower electrode portion covering an upper surface of the supporting conductor, the additional lower electrode portion comprising a different material from the supporting conductor, and wherein forming the capacitor dielectric layer includes forming the capacitor dielectric layer on the additional lower electrode portion, and wherein the lower electrode includes a conductive material and wherein the lower electrode comprises a noble metal, a conductive oxide of a noble metal and/or a perovskite structure conductive oxide deposited in an oxidative ambient and wherein the supporting conductor comprises a refractory metal and/or a conductive nitride deposited in a reductive ambient.

2. The method of claim 1 , wherein forming the lower electrode comprises:

forming a lower insulating layer on the substrate;

forming a contact hole through the lower insulating layer;

forming the contact plug in the contact hole;

forming an upper insulating layer on the lower insulating layer including the contact plug;

forming an opening in the upper insulating layer over the contact plug without exposing the contact plug;

forming the lower electrode on sidewalls of the opening in the upper insulating layer; and

exposing the contact plug by extending the opening in the upper insulating layer after forming the lower electrode.

3. The method of claim 2 , wherein forming a supporting conductor comprises forming the supporting conductor to a height lower than an upper surface of the lower electrode to provide an electrode space and wherein forming the additional lower electrode portion comprises forming the additional lower electrode portion in the electrode space and contacting the lower electrode formed on the sidewalls of the opening in the upper insulating layer.

4. The method of claim 3 , wherein forming the supporting conductor to a height lower than an upper surface of the lower electrode comprises:

depositing a material layer of the material of the supporting conductor on the upper insulating layer and the supporting conductor;

polishing the deposited material layer to expose the upper insulating layer; and then

etching the polished supporting conductor to form the electrode space.

5. The method of claim 3 , wherein forming the additional lower electrode portion comprises depositing a ruthenium layer in the electrode space using a physical vapor deposition (PVD) process in an oxygen free atmosphere.

6. The method of claim 1 , wherein forming the supporting conductor comprises forming the supporting conductor of a material different from a material of the lower electrode.

7. The method of claim 3 , wherein the lower electrode comprises a material including a noble metal and wherein the supporting conductor comprises a material selected to have a higher adhesion than the material of the lower electrode to the first upper insulating layer and the lower insulating layer to limit oxidation and/or etchant damage of the contact plug during forming of the capacitor:

8. The method of claim 7 , wherein the first upper insulating layer comprises silicon nitride and/or tantalum oxide and the lower insulating layer comprises silicon oxide.

9. The method of claim 1 , wherein the contact plug comprises doped polysilicon.

10. The method of claim 1 , wherein forming the lower electrode comprises forming the lower electrode using chemical vapor deposition (CVD) and/or atomic layer deposition (ALD) in an oxidizing ambient.

11. A method of forming a capacitor of an integrated circuit device, comprising:

forming a lower electrode of the capacitor on an integrated circuit substrate without exposing a contact plug to be coupled to the lower electrode;

forming a supporting conductor coupling the lower electrode to the contact plug after forming the lower electrode;

forming a capacitor dielectric layer on the lower electrode; and

forming an upper electrode of the capacitor on the capacitor dielectric layer,

wherein forming the capacitor dielectric layer is preceded by forming an additional lower electrode portion covering an upper surface of the supporting conductor, the additional lower electrode portion comprising a different material from the supporting conductor, and wherein forming the capacitor dielectric layer includes forming the capacitor dielectric layer on the additional lower electrode portion,

wherein forming a supporting conductor comprises forming the supporting conductor to a height lower than an upper surface of the lower electrode to provide an electrode space and wherein forming the additional lower electrode portion comprises forming the additional lower electrode portion in the electrode space and contacting the lower electrode formed on the sidewalls of the opening in the upper insulating layer,

wherein the capacitor is located in a cell area of the integrated circuit device and wherein the integrated circuit device also includes a peripheral area and wherein forming the supporting conductor to a height lower than an upper surface of the lower electrode comprises:

depositing a material layer of the material of the additional lower electrode portion on an upper insulating layer of the integrated circuit device and the supporting conductor in the cell area and on an insulating layer in the peripheral area, where a thickness of the material layer is less on the cell area than on the peripheral area; and

etching back the deposited material layer to expose the insulating layer of the peripheral area and the upper insulating layer in the cell area and to form the electrode space.