Method to increase breakdown voltage of semiconductor devices
Methods of achieving high breakdown voltages in semiconductor devices by suppressing the surface flashover using high dielectric strength insulating encapsulation material are generally described. In one embodiment of the present invention, surface flashover in AlGaN/GaN heterostructure field-effect transistors (HFETs) is suppressed by using high dielectric strength insulating encapsulation material. Surface flashover in as-fabricated III-Nitride based HFETs limits the operating voltages at levels well below the breakdown voltages of GaN.
1. A method of fabricating a high breakdown voltage semiconductor device comprising
providing a semiconductor device defining a top surface area formed by a GaN layer, the semiconductor device having a source electrode, a drain electrode and a AlGaN layer on the top surface, wherein the AlGaN layer is positioned between the source electrode and the drain electrode, and wherein a gate overlies the AlGaN layer; and
depositing a high dielectric strength insulating material over the entire top surface area including the source electrode, the drain electrode, and the gate leaving only leads connected to the device uncovered by the high dielectric strength insulating material, wherein the high dielectric strength insulating material is deposited to a thickness of 500 Å to about 10 μm about to suppress surface flashover.
2. The method according to claim 1 , wherein the high dielectric strength insulating material has a dielectric strength greater than air.
3. The method according to claim 2 , wherein said high dielectric strength insulating material comprises silicon dioxide, silicon nitride, strontrium titanate, benzocyclobutene, aluminium nitride, aluminum galium nitride, galium nitride, boron nitride, silicon carbide, diamond, aluminum oxide, magnesium oxide, hafnium oxide, zirconium oxide, scandium oxide, polytetrafluoroethylene, perfluoroalkoxy, fluorinated ethylene propylene, polystyrene, silicone oil, nylon, polyoxybenzylmethylenglycolanhydride, or combinations thereof.
4. The method of claim 3 , wherein said high dielectric strength insulating material is a single layer or a multi stack layer deposited using digital dielectric deposition method.
5. The method according to claim 1 , wherein said semiconductor device having a high breakdown voltage comprising silicon carbide, gallium nitride, aluminum gallium nitride, aluminum indium gallium nitride, diamond, aluminum nitride or combinations thereof.
6. The method according to claim 1 , wherein said semiconductor device is a heterostructure field-effect transistor.
7. The method according to claim 1 , wherein said semiconductor device is a MOSFET.
8. The method of claim 1 , wherein the high dielectric strength insulating material is deposited to a thickness of about 0.3 μm to about 10 μm.
9. The method of claim 1 , wherein the high dielectric strength insulating material comprises silicone dioxide and is deposited to a thickness of about 0.2 μm to about 0.5 μm.
10. The method of claim 1 , wherein the high dielectric strength insulating material comprises benzocyclobutene.
11. A method of fabricating a high breakdown voltage semiconductor device comprising
providing a semiconductor device defining a top surface area formed by a GaN layer, the semiconductor device having a source electrode, a drain electrode and a AlGaN layer on the top surface, wherein the AlGaN layer is positioned between the source electrode and the drain electrode, and wherein a gate overlies the AlGaN layer; and
depositing a high dielectric strength insulating material over at least a portion of the top surface area including the source electrode, the drain electrode, and the gate, wherein the high dielectric strength insulating material comprises benzocyclobutene and is deposited to a thickness of about 500 Å to about 10 μm to suppress surface flashover.
12. The method of claim 11 , wherein said high dielectric strength insulating material is a single layer or a multi stack layer deposited using digital dielectric deposition method.
13. The method of claim 11 , wherein said semiconductor device is a heterostructure field-effect transistor.
14. The method of claim 11 , wherein said semiconductor device is a MOSFET.
15. The method of claim 11 , wherein the high dielectric strength insulating material is deposited to a thickness of about 0.3 μm to about 10 μm.
16. The method of claim 11 , wherein the high dielectric strength insulating material is deposited on the top surface between the drain electrode and the gate.
17. The method of claim 11 , wherein the high dielectric strength insulating material is deposited on the top surface between the source electrode and the gate.