Method of reading memory cell
View Patent ↗A method for reading a memory cell ( 20 ) of a semiconductor memory ( 10 ) includes initiating a precharge or predischarge operation on a bit line ( 24 ) prior to arrival of a triggering edge of a clock signal ( 32 ) that initiates a read operation. A word line ( 22 ) is activated responsive to the triggering edge of the clock signal ( 32 ), and data is read from the memory cell ( 20 ).
1. A precharge circuit for precharging a bit line of a semiconductor memory device, the precharge circuit comprising:
a plurality of series connected inverters for generating a latch signal;
a first feedback inverter having an input connected to a last inverter of the plurality of series connected inverters and an output connected to an input of the last inverter of the plurality of series connected inverters;
a first reset transistor connected between the output of said last inverter and a first supply voltage, and having a gate that receives a reset clock signal;
a first transistor having a gate that receives the latch signal;
a second transistor connected between the first transistor and a second supply voltage;
a second reset transistor connected between the first transistor and the first supply voltage, and having a gate that receives the reset clock signal;
a common precharge inverter having an input connected to a first node between the first transistor and the second reset transistor, and an output that provides a common precharge signal;
a second feedback inverter having an input connected to the output of the common precharge inverter and an output connected to the first node;
a third feedback inverter having an input connected to the output of the common precharge inverter and an output connected to a gate of the second transistor;
a logic gate having a first input connected to the output of the common precharge inverter for receiving the common precharge signal, and an output that provides a precharge pulse;
a first precharge clock inverter having an input connected to the output of the common precharge inverter for receiving the common precharge signal, and an output that provides a precharge clock signal;
a second precharge clock inverter having an input connected to the output of the first precharge clock inverter;
a fifth transistor having a gate connected to an output of the second precharge clock inverter, and a source connected to the first power supply;
a sixth transistor having a gate connected to a reference bit line of the semiconductor memory, and a drain connected to a drain of the fifth transistor;
a seventh transistor having a drain connected to a drain of the fifth transistor; and
a programmable delay circuit that has an input connected to the drain of the fifth transistor and an output connected to a second input of the logic gate.
2. The precharge circuit of claim 1 , further comprising a reference bit line precharge circuit connected to the reference bit line, the reference bit line precharge circuit comprising:
a third transistor connected to the first precharge clock inverter and having a gate that receives the precharge clock signal; and
a fourth transistor connected to the logic gate and having a gate that receives the precharge pulse, wherein the reference bit line is connected to a node between the third and fourth transistors.
3. The precharge circuit of claim 2 , wherein the third transistor is a NMOS transistor and the fourth transistor is a PMOS transistor, wherein the third transistor has a drain connected to the second power supply, and the fourth transistor has a source connected to the first power supply and a drain connected to a source of the third transistor.
4. The precharge circuit of claim 1 , wherein the first inverter in the series receives a chip enable signal and the last inverter in the series outputs the latch signal.
5. The precharge circuit of claim 4 , wherein the plurality of series connected inverters comprises four inverters.
6. The precharge circuit of claim 4 , wherein the first reset transistor is a PMOS transistor.
7. The precharge circuit of claim 6 , wherein the first transistor and second transistors comprise NMOS transistors.
8. The precharge circuit of claim 7 , wherein the second reset transistor is a PMOS transistor.
9. The precharge circuit of claim 4 , wherein the first power supply comprises a positive voltage supply and the second power supply comprises a ground.
10. The precharge circuit of claim 4 , wherein the precharge clock signal initiates precharging of the bit line.
11. The precharge circuit of claim 10 , wherein the precharge pulse terminates the precharging of the bit line.
12. The precharge circuit of claim 4 , wherein the logic gate comprises a NAND gate.
13. The precharge circuit of claim 1 , wherein the fifth transistor has a source connected to the first power supply, and the sixth transistor has a source connected to the second power supply.
14. The precharge circuit of claim 1 , wherein the programmable delay circuit comprises two or more series connected inverters.
15. The precharge circuit of claim 14 , wherein a gate of the seventh transistor is connected to an output of a first one of the two or more series connected inverters.