IP Library Granted Patent US 8,327,065
Granted Patent B2
US 8,327,065 · App. 12/566,236 · Granted Dec 4, 2012

Memory system, controller, and method of controlling memory system

Assignee: Kabushiki Kaisha Toshiba
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Quick Facts
Patent No.
US 8,327,065
App. No.
12/566,236
Granted
Dec 4, 2012
Kind
B2
Abstract

A memory system according to an embodiment of the present invention includes a volatile first storing unit, a nonvolatile second storing unit, a controller that transfers data between a host apparatus and the second storing unit via the first storing unit. The memory system monitors whether data written from the host apparatus in the first storing unit has a specific pattern in management units. When data to be flushed to the second storing unit has the specific pattern, the memory system set an invalid address value that is not in use in the second storing unit to the data.

Claims (43)

1. A memory system comprising:

a volatile first storing unit;

a nonvolatile second storing unit; and

a controller that transfers data between a host apparatus and the second storing unit via the first storing unit, wherein

the first storing unit stores therein first management information used for correlating a logical address designated by the host apparatus with a data storage location in the first storing unit, and second management information used for correlating the logical address and a data storage location in the second storing unit,

the controller further includes

a read-write control unit that performs data reading and data writing between the host apparatus and the first storing unit and between the first storing unit and the second storing unit, by using the first management information and the second management information;

a management-information updating unit that updates the first or the second management information when the data storage location in the first or the second storing unit is changed by the read-write control unit; and

a data monitoring unit that monitors whether data written in the first storing unit from the host apparatus has a specific pattern with respect to each specific management unit, wherein

when the data monitoring unit detects that data having the specific pattern is written in the first storing unit, the management-information updating unit adds specific pattern identification information indicating that the data has the specific pattern to the first management information corresponding to the data, and

when data written in the first storing unit is flushed to the second storing unit, and if the specific pattern identification information is added for the data, the read-write control unit does not write the data in the second storing unit, and the management-information updating unit sets an invalid address value to the second management information corresponding to the data.

2. The memory system according to claim 1 , wherein when a logical address designated by the host apparatus is associated with the invalid address value set to the second management information, the read-write control unit returns data having the specific pattern and associated with the invalid address value to the host apparatus via the first storing unit without reading data from a data storage location associated with the logical address of the second storing unit.

3. The memory system according to claim 1 , wherein the specific pattern corresponds to a state where all bits of data in the management unit are uniformly set to either zero or one.

4. The memory system according to claim 1 , wherein the management-information updating unit sets, as the invalid address value, an address value that is not associated with hardware used in the memory system.

5. The memory system according to claim 1 , wherein the data monitoring unit monitors data sent between the host apparatus and the first storing unit.

6. The memory system according to claim 1 , wherein the data monitoring unit monitors data written in the first storing unit.

7. The memory system according to claim 1 , wherein the data monitoring unit monitors data sent between the first storing unit and the controller.

8. The memory system according to claim 1 , wherein

the first storing unit is a dynamic random access memory, and

the second storing unit is a NAND type flash memory.

9. A controller that transfers data between a host apparatus and a nonvolatile second storing unit via a volatile first storing unit, the controller comprising:

a read-write control unit that performs data reading and data writing between a host apparatus and the first storing unit and between the first storing unit and the second storing unit, by using first management information used for correlating a logical address designated by the host apparatus with a data storage location in the first storing unit and second management information used for correlating the logical address with a data storage location in the second storing unit;

a management-information updating unit that updates the first or the second management information when the data storage location in the first or the second storing unit is changed by the read-write control unit; and

a data monitoring unit that monitors whether data written in the first storing unit from the host apparatus has a specific pattern with respect to each specific management unit, wherein

when the data monitoring unit detects that data having the specific pattern is written in the first storing unit, the management-information updating unit adds specific pattern identification information indicating that the data has the specific pattern to the first management information corresponding to the data, and

when data written in the first storing unit is flushed to the second storing unit, and if the specific pattern identification information is added for the data, the read-write control unit does not write the data in the second storing unit, and the management-information updating unit sets an invalid address value to the second management information corresponding to the data.

10. The controller according to claim 9 , wherein when a logical address designated by the host apparatus is associated with the invalid address value set to the second management information, the read-write control unit returns data having the specific pattern and associated with the invalid address value to the host apparatus via the first storing unit without reading data from a data storage location associated with the logical address in the second storing unit.

11. The controller according to claim 9 , wherein the specific pattern corresponds to a state where all bits of data in the management unit are uniformly set to either zero or one.

12. The controller according to claim 9 , wherein the management-information updating unit sets, as the invalid address value, an address value that is not associated with hardware used in the memory system.

13. The controller according to claim 9 , wherein the data monitoring unit monitors data sent between the host apparatus and the first storing unit.

14. The controller according to claim 9 , wherein the data monitoring unit monitors data written in the first storing unit.

15. The controller according to claim 9 , wherein the data monitoring unit monitors data sent between the first storing unit and the controller.

16. A method of controlling a memory system that includes a volatile first storing unit and a nonvolatile second storing unit comprising:

transferring data between a host apparatus and the second storing unit via the first storing unit;

performing data reading and data writing between a host apparatus and the first storing unit and between the first storing unit and the second storing unit, by using first management information being used for correlating a logical address designated by the host apparatus with a data storage location in the first storing unit and second management information being used for correlating the logical address with a data storage location in the second storing unit;

updating the first or the second management information when the data storage location in the first or the second storing unit is changed at the performing;

monitoring whether data written in the first storing unit from the host apparatus has a specific pattern with respect to each specific management unit;

adding, when it is detected at the monitoring that data having the specific pattern is written in the first storing unit, specific pattern identification information indicating that the data has the specific pattern to first management information corresponding to the data; and

setting, when data written in the first storing unit is flushed to the second storing unit and if the specific pattern identification information is added for the data, an invalid address value to the second management information corresponding to the data without writing the data in the second storing unit.

17. The method according to claim 16 , further comprising returning, when a logical address designated by the host apparatus is associated with the invalid address value set to the second management information, data having the specific pattern and associated with the invalid address value to the host apparatus via the first storing unit without reading data from a data storage location associated with the logical address in the second storing unit.

18. The method according to claim 16 , wherein the specific pattern corresponds to a state where all bits in data in the management unit are uniformly set to either zero or one.

19. The method according to claim 16 , further comprising setting, as the invalid address value, an address value that is not associated with hardware used in the memory system.

20. The memory system according to claim 16 , further comprising monitoring data sent between the host apparatus and the first storing unit.

Assignments (5)
CHANGE OF NAME AND ADDRESS Recorded Jan 22, 2021
From: K.K. PANGEA
To: TOSHIBA MEMORY CORPORATION
Reel/Frame 055669/0401 →
MERGER Recorded Jan 22, 2021
From: TOSHIBA MEMORY CORPORATION
To: K.K. PANGEA
Reel/Frame 055659/0471 →
CHANGE OF NAME AND ADDRESS Recorded Jan 22, 2021
From: TOSHIBA MEMORY CORPORATION
To: KIOXIA CORPORATION
Reel/Frame 055669/0001 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Aug 24, 2017
From: KABUSHIKI KAISHA TOSHIBA
To: TOSHIBA MEMORY CORPORATION
Reel/Frame 043709/0035 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Dec 1, 2009
From: YANO, HIROKUNI; KANNO, SHINICHI
To: KABUSHIKI KAISHA TOSHIBA
Reel/Frame 023582/0433 →
Priority Claims (1)
JP 2008-335543 · Dec 27, 2008 · national
Continuity (1)
Related Publication 20100169553A1 · Jul 1, 2010