Shielded gate trench FET with an inter-electrode dielectric having a low-k dielectric therein
A method for forming a shielded gate trench field effect transistor (FET) includes forming trenches in a semiconductor region, forming a shield electrode in a bottom portion of each trench, and forming an inter-electrode dielectric (IED) extending over the shield electrode. The IED may comprise a low-k dielectric. The method also includes forming a gate electrode in an upper portion of each trench over the IED.
1. A method for forming a shielded gate trench field effect transistor (FET), the method comprising:
forming a trench in a semiconductor region;
forming a shield electrode on a bottom surface of the trench;
forming an inter-electrode dielectric (IED) on an exposed surface of the shield electrode, the IED including a low-k dielectric;
forming a gate dielectric lining at least one of a sidewall of the trench and an exposed surface of the IED;
forming a conductive liner layer on an exposed surface of the gate dielectric; and
forming a gate electrode on an exposed surface of the conductive liner layer.
2. The method of claim 1 further comprising forming a high-k dielectric, at least a portion of the high-k dielectric being disposed between the low-k dielectric and the conductive liner layer.
3. The method of claim 1 wherein the gate electrode includes a metal.
4. The method of claim 1 wherein forming the IED includes forming an insulating material such that the low-k dielectric extends along a side surface and a bottom surface of the insulating material.
5. The method of claim 4 wherein the insulating material includes an undoped oxide.
6. A method for forming a shielded gate trench field effect transistor (FET), the method comprising:
forming a trench in a semiconductor region;
forming a shield electrode on a bottom surface of the trench;
forming an inter-electrode dielectric (IED) on an exposed surface of the shield electrode;
forming a gate dielectric lining at least one of a sidewall of the trench and an exposed surface of the IED, the gate dielectric including a high-k dielectric having a concentration of oxide, the concentration of oxide being graded along a thickness of the high-k dielectric and being highest in a portion of the high-k dielectric nearest the semiconductor region; and
forming a gate electrode disposed above the gate dielectric.
7. The method of claim 6 wherein the gate dielectric further includes a thermal oxide.
8. The method of claim 1 wherein the semiconductor region includes an epitaxial layer of a first conductivity type disposed over a substrate, the method further comprising:
prior to forming the IED, forming a body region of a second conductivity type extending into the epitaxial layer;
prior to forming the IED, forming source regions of the first conductivity type adjacent to the trench in the body region; and
forming a conductor layer extending over the semiconductor region, the conductor layer contacting the source regions and being isolated from the gate electrode by a dielectric cap.
9. The method of claim 8 further comprising:
forming a dielectric liner, at least a portion of the dielectric liner being disposed between the gate electrode and the dielectric cap, the dielectric liner including nitride.
10. The method of claim 6 wherein at least a portion of the high-k dielectric is disposed between the IED and the gate electrode.
11. The method of claim 1 wherein the gate dielectric includes a high-k dielectric having a concentration of oxide, the concentration of oxide being graded along a thickness of the high-k dielectric.
12. The method of claim 6 wherein the IED includes a low-k dielectric and forming the IED includes forming an insulating material such that the low-k dielectric extends along a side surface and a bottom surface of the insulating material.
13. The method of claim 6 wherein the gate dielectric further includes a thermal oxide disposed between the high-k dielectric and the sidewall of the trench.
14. The method of claim 6 further comprising forming a conductive liner layer disposed between the gate dielectric and the gate electrode.
15. The method of claim 6 wherein the semiconductor region includes an epitaxial layer of a first conductivity type disposed over a substrate, the method further comprising:
prior to forming the IED, forming a body region of a second conductivity type extending into the epitaxial layer; and
prior to forming the IED, forming source regions of the first conductivity type adjacent to the trench in the body region.
16. The method of claim 6 further comprising:
forming a conductor layer extending over the semiconductor region, the conductor layer contacting a source region of the trench FET and being isolated from the gate electrode by a dielectric cap; and
forming a dielectric liner, at least a portion of the dielectric liner being disposed between the gate electrode and the dielectric cap, the dielectric liner including nitride.