Modified profile gate structure for semiconductor device and methods of forming thereof

1. A method of fabricating a semiconductor device, comprising:

providing a substrate;

forming a dummy gate structure on the substrate, wherein the dummy gate structure includes a first layer of a dummy gate electrode, an intermediate layer on the first layer and a second layer of the dummy gate electrode on the intermediate layer;

forming a first spacer element abutting the dummy gate structure, wherein the first spacer element and the intermediate layer have substantially the same composition;

forming a modified profile opening on the substrate by removing at least a portion of the dummy gate structure and a portion of the first spacer element, wherein the modified profile opening includes a first width proximate a surface of the substrate and a second width opposing the substrate, the second width being greater than the first width; and

forming a metal gate electrode, wherein the forming the metal gate electrode includes filling the modified profile opening with a conductive material.

2. The method of claim 1 , wherein the modified profile opening includes a first portion having arcuate sidewalls.

3. The method of claim 2 , wherein the second width is disposed in the first portion.

4. The method of claim 1 , wherein the forming the modified profile opening includes:

performing a first etch process, wherein the first etch process removes a portion of the first spacer element and the intermediate layer; and

performing a second etch process, following the first etch process, wherein the second etch process removes the first layer of the dummy gate electrode.

5. The method of claim 4 , wherein the first etch process removes a portion of a contact etch stop layer.

6. The method of claim 1 , further comprising:

forming a high-k gate dielectric layer in the modified profile opening prior to forming the metal gate electrode.

7. The method of claim 1 , further comprising:

forming a second spacer element adjacent the first spacer element, wherein the second spacer element has a different composition that the first spacer element.

8. A method, comprising:

providing a semiconductor substrate;

forming a dummy gate structure on the semiconductor substrate;

forming a spacer element adjacent the dummy gate structure;

forming an etch stop layer on the spacer element;

etching the spacer element and etch stop layer to provide a first opening of a first width prior to removing the dummy gate structure;

thereafter removing the dummy gate structure to provide a second opening of a second width, wherein the second width is less than the first width, and wherein the first and second opening are continual and form a modified profile opening; and

forming a metal gate electrode in the modified profile opening.

9. The method of claim 7 , forming a modified profile opening on the substrate by removing the at least a portion of the dummy gate structure and the portion of the first spacer element includes:

performing an etch process, wherein the etch process removes the portion of the first spacer element and the intermediate layer of the dummy gate structure to create a first opening, wherein the first opening is defined by the sidewalls of the second spacer element.

10. The method of claim 1 , wherein forming the modified profile opening by removing the at least a portion of the dummy gate structure and the portion of the first spacer element includes:

removing the second layer of the dummy gate electrode;

thereafter, removing the intermediate layer of the dummy gate structure concurrently with removing the portion of the first spacer element; and

thereafter, removing the first layer of the dummy gate electrode.

11. The method of claim 1 , wherein the intermediate layer is selected from the group consisting of silicon oxide, silicon nitride, silicon oxynitride, silicon carbide, fluoride-doped silicate glass (FSG), a low k dielectric material, and combinations thereof.

12. The method of claim 8 , wherein the first opening includes arcuate sidewalls.

13. The method of claim 8 , wherein the second opening includes substantially straight sidewalls.

14. The method of claim 8 , further comprising:

forming an interlayer dielectric (ILD) layer on the etch stop layer; and

prior to etching the spacer element and etch stop layer, removing a portion of the ILD layer such that a top surface of the ILD layer is below a top surface of the dummy gate structure.

15. A method of fabricating a semiconductor device, comprising:

forming a dummy gate structure on the substrate, wherein the dummy gate structure includes a first layer of a dummy gate electrode, an intermediate layer on the first layer and a second layer of the dummy gate electrode on the intermediate layer;

forming a first spacer element abutting the dummy gate structure;

forming a second spacer element adjacent the first spacer element;

forming a modified profile opening on the substrate, wherein the forming the modified opening includes:

performing a first etch process to remove the second layer of the dummy gate electrode;

thereafter, performing a second etch process to remove the intermediate layer and a portion of the first spacer element; and

thereafter, performing a third etch process to remove the first layer of the dummy gate electrode; and

forming a gate structure in the modified profile opening.

16. The method of fabricating a semiconductor device of claim 15 , wherein the removing the intermediate layer and the portion of the first spacer element profile provides an opening defined by a sidewall of the second spacer element.

17. The method of fabricating a semiconductor device of claim 15 , wherein the removing the intermediate layer and the portion of the first spacer element profile provides a first portion of the modified profile opening and wherein the removing the first layer of the dummy gate electrode provides a second portion of the modified profile opening, and wherein the first portion has a greater width than the second portion.

18. The method of fabricating a semiconductor device of claim 15 , wherein at least one layer of the gate structure directly interfaces the second spacer element.

19. The method of fabricating a semiconductor device of claim 15 , wherein the second spacer element includes a material that has an etch selectivity to the second etch process such that the second spacer element is not removed by the second etch process.

20. The method of fabricating a semiconductor device of claim 15 , wherein the intermediate layer and the first spacer element are the same dielectric material.