Semiconductor device having a reduced bit line parasitic capacitance and method for manufacturing the same
A semiconductor device having a reduced bit line parasitic capacitance and a method of making same is presented. The semiconductor device includes a first, second, third, and fourth interlayer dielectric layers, first and second bit lines, first and second landing plug and first and second storage node contacts. An optional capacitor may be added to complete a CMOS configuration for the semiconductor device. The storage node contacts traverse through the interlayer dielectric layer and are electrically coupled to their respective landing plug contacts. The storage node contacts are deliberately offset, relative to the center of the corresponding landing plug contacts, at a predetermined distance in a direction away from the first bit line. This offsetting aids reducing the parasitic capacitance between the bit line and a storage node.
1. A semiconductor device comprising:
a first interlayer dielectric (ID 1 ) on a substrate;
first bit lines (BL 1 ) on the ID 1 that extend substantially along a first direction on the ID 1 ;
a second interlayer dielectric (ID 2 ) covering the BL 1 ;
a third interlayer dielectric (ID 3 ) on the ID 2 ;
second bit lines (BL 2 ) on the ID 3 that extend substantially along the first direction so that the BL 2 on the ID 3 are substantially in parallel to the BL 1 on the ID 1 and are aligned between the BL 1 ;
a fourth interlayer dielectric (ID 4 ) covering the BL 2 ;
first landing plug contacts (LPC 1 ) through the ID 1 and connected to the substrate;
first storage node contacts (SNC 1 ) through the ID 2 and electrically coupled to the LPC 1 wherein the SNC 1 are offset at a first predetermined width (W 1 ) from the LPC 1 in a direction away from the BL 1 ;
second landing plug contacts (LPC 2 ) through the ID 3 and electrically coupled to the SNC 1 ; and
second storage node contacts (SNC 2 ) through the ID 4 and electrically coupled to the LPC 2 wherein the SNC 2 are offset at a second predetermined width (W 2 ) from the LPC 2 in a direction away from the BL 2 , wherein the second landing plug contacts LPC 2 that are electrically coupled to the first storage node contacts SNC 1 are electrically coupled to the first bit lines BL 1 and the second landing plug contacts LPC 2 that are electrically coupled to SNC 2 wherein the SNC 2 are offset at a second predetermined width (W 2 ) from the LPC 2 in a direction away from the BL 2 .
2. The semiconductor device according to claim 1 , further comprising:
first bit line contacts (BLC 1 ) through the ID 1 and connected to the substrate and electrically coupled to the BL 1 ; and
second bit line contacts (BLC 2 ) through the ID 1 , ID 2 , and ID 3 and connected to the substrate and electrically coupled to the BL 2 .
3. The semiconductor device according to claim 1 , wherein the ID 2 and ID 4 are composed of oxide layer.
4. The semiconductor device according to claim 1 , further comprising
spacers between the LPC 1 and the ID 1 ;
spacers between the SNC 1 and the ID 2 ;
spacers between the LPC 2 and the ID 3 ; and
spacers between the SNC 2 and the ID 4 .