Interconnect structure for semiconductor devices

1. A semiconductor device comprising:

a first dielectric layer on a substrate, the first dielectric layer having a conductive layer formed therein, the conductive layer comprising a first material and having a recess, the first material comprising a metal; and

an alloy layer at least partially within the recess, the alloy layer being a suicide alloy comprising the first material and a second material, the second material comprising germanium, arsenic, tungsten, or gallium.

2. The semiconductor device of claim 1 , further comprising a seed layer between the conductive layer and the alloy layer.

3. The semiconductor device of claim 1 , wherein the first material comprises copper.

4. The semiconductor device of claim 1 , further comprising a second dielectric layer directly over the alloy layer.

5. The semiconductor device of claim 1 , further comprising:

an etch stop layer over the alloy layer and the first dielectric layer, and

a second dielectric layer over the etch stop layer.

6. The semiconductor device of claim 1 , further comprising a barrier layer interposed between the conductive layer and sidewalls of the first dielectric layer.

7. The semiconductor device of claim 6 , wherein the alloy layer extends over the barrier layer.

8. A semiconductor device comprising:

a conductive layer within a substrate, the conductive layer comprising a first material and having a first top surface, the substrate having a second top surface planar to the first top surface;

an alloy layer overlying the conductive layer, the alloy layer having a third top surface that is planar, the alloy layer being a suicide alloy comprising the first material and a second material, the second material comprising germanium, arsenic, tungsten, or gallium; and

a seed layer between the conductive layer and the alloy layer.

9. The semiconductor device of claim 8 , wherein the first material comprises copper.

10. The semiconductor device of claim 8 , further comprising a second dielectric layer directly over the alloy layer.

11. The semiconductor device of claim 8 , further comprising:

an etch stop layer over the alloy layer and the substrate, and

a second dielectric layer over the etch stop layer.

12. The semiconductor device of claim 8 , further comprising a barrier layer interposed between the conductive layer and sidewalls of the substrate.

13. The semiconductor device of claim 8 , wherein the substrate comprises a low-k dielectric.

14. A semiconductor device comprising:

a first dielectric layer on a substrate, the first dielectric layer having a top surface;

a conductive layer extending through the dielectric layer, the conductive layer having a convex surface that extends beyond the top surface, the conductive layer comprising a metallic first material; and

an alloy layer located con formally to the convex surface, the alloy layer being a silicide and comprising the metallic first material and a second material, the second material comprising germanium, arsenic, tungsten, or gallium.

15. The semiconductor device of claim 14 , further comprising a seed layer between the conductive layer and the alloy layer.

16. The semiconductor device of claim 14 , wherein the first material comprises copper.

17. The semiconductor device of claim 14 , further comprising a second dielectric layer directly over the alloy layer.

18. The semiconductor device of claim 14 , further comprising a barrier layer interposed between the conductive layer and sidewalls of the first dielectric layer.

19. The semiconductor device of claim 18 , wherein the alloy layer extends over the barrier layer.