FPGA with hybrid interconnect
An Application-Specific Field Programmable Gate Array (FPGA) device or fabric is described for use in applications requiring fast reconfigurability of devices in the field, enabling multiple personalities for re-using silicon resources (like arrays of large multipliers in DSP applications) from moment-to-moment for implementing different hardware algorithms. In a general purpose FPGA device or fabric, this fast reconfigurability is normally implemented by special reconfiguration support circuitry and/or additional configuration memory. Unfortunately, this flexibility requires a large amount of programmable routing resource and silicon area—limiting the viability in volume production applications. This invention describes how multi-program FPGA functionalities may be migrated to smaller die by constructing implementations with a hybrid FPGA/ASIC interconnect structure. These implementations retain multi-program capability while requiring a much smaller silicon area than a conventional FPGA when customized for a particular set of user applications.
1. A hybrid application-specific and field-programmable integrated circuit, comprising:
a die;
a plurality of non-reprogrammable circuit elements disposed on the die; and
a first and a second plurality of reprogrammable circuit elements disposed on the die, wherein:
the first plurality of reprogrammable circuit elements are configurable to be coupled with each other and with the plurality of non-reprogrammable circuit elements to implement a first application; and
the second plurality of reprogrammable circuit elements are configurable to be coupled with each other and with the plurality of non-reprogrammable circuit elements to implement a second application, wherein the first and second applications are different applications.
2. The hybrid application-specific and field-programmable integrated circuit of claim 1 , wherein:
the first plurality of reprogrammable circuit elements comprises a first plurality of field-programmable switches; and
the second plurality of reprogrammable circuit elements comprises a second plurality of field-programmable switches.
3. The hybrid application-specific and field-programmable integrated circuit of claim 1 , further comprising a plurality of reprogrammable logic cells including a first subset coupled to the first plurality of reprogrammable circuit elements to implement the first application, and a second field-reconfigured subset coupled to the second plurality of reprogrammable circuit elements to implement the second application.
4. The hybrid application-specific and field-programmable integrated circuit of claim 3 , wherein the reprogrammable logic cells comprise a plurality of field-programmable gate array (FPGA) logic cells.
5. A hybrid application-specific and field-programmable integrated circuit, comprising:
a die;
a plurality of logic cells disposed on the die;
a first set of interconnects disposed on the die to implement a first application; and
a second set of interconnects disposed on the die to implement a second application, wherein:
the first set of interconnects comprises a first reprogrammable interconnect to operatively couple a first pair of the plurality of logic cells disposed on the die;
the second set of interconnects comprises a second reprogrammable interconnect to operatively couple a second pair of the plurality of logic cells disposed on the die; and
both the first set of interconnects and the second set of interconnects share a common non-reprogrammable interconnect to operatively couple a third pair of the plurality of logic cells.
6. The hybrid application-specific and field-programmable integrated circuit of claim 5 , wherein:
the first reprogrammable interconnect comprises a first field-programmable switch; and
the second reprogrammable interconnect comprises a second field-programmable switch.
7. The hybrid application-specific and field-programmable integrated circuit of claim 5 , wherein the plurality of logic cells comprises a field-programmable gate array (FPGA) logic cell.
8. The hybrid application-specific and field-programmable integrated circuit of claim 5 , further comprising a memory cell, wherein the first set of interconnects further couple the memory cell to the first pair of the plurality of logic cells.
9. A hybrid application-specific and field-programmable integrated circuit, comprising:
a die;
a first plurality of reprogrammable circuit elements disposed on the die;
a second plurality of reprogrammable circuit elements disposed on the die; and
a plurality of non-reprogrammable circuit elements arranged to form:
part of a first application upon activation of the first plurality of reprogrammable circuit elements; and
part of a second application upon activation of the second plurality of reprogrammable circuit elements.
10. The hybrid application-specific and field-programmable integrated circuit of claim 9 , wherein the plurality of non-reprogrammable circuit elements are arranged to form:
part of the first application upon deactivation of the second plurality of reprogrammable circuit elements; and
part of the second application upon deactivation of the first plurality of reprogrammable circuit elements.
11. The hybrid application-specific and field-programmable integrated circuit of claim 10 , wherein the first and second pluralities of logic cells share a programmable logic cell.
12. The hybrid application-specific and field-programmable integrated circuit of claim 10 , wherein:
the first plurality of reprogrammable circuit elements comprises a first field-programmable switch; and
the second plurality of reprogrammable circuit elements comprises a second field-programmable switch.
13. The hybrid application-specific and field-programmable integrated circuit of claim 9 , further comprising:
a first plurality of programmable logic cells coupled to the first plurality of reprogrammable circuit elements and to the plurality of non-reprogrammable circuit elements, wherein the first plurality of programmable logic cells are configurable to partly implement the second application; and
a second plurality of programmable logic cells coupled to the second plurality of reprogrammable circuit elements and to the plurality of non-reprogrammable circuit elements, wherein the second plurality of programmable logic cells are configurable to partly implement the second application.
14. The hybrid application-specific and field-programmable integrated circuit of claim 9 further comprising a memory cell, wherein the first plurality of reprogrammable circuit elements further couple the memory cell to the plurality of non-reprogrammable circuit elements.