Method for fabricating semiconductor device with buried gates
A method for fabricating a semiconductor device includes providing a substrate including cell regions and peripheral regions; selectively forming a gate conductive layer over the substrate in the peripheral regions, forming a sealing layer over the substrate with the gate conductive layer formed thereon, forming an insulation layer over the sealing layer to cover the substrate with the gate conductive layer formed on the substrate, planarizing the insulation layer to expose the sealing layer formed over the gate conductive layer, and forming a plurality of plugs in the cell regions, the plurality of the plugs penetrating the insulation layer and the sealing layer.
1. A method for fabricating a semiconductor device, comprising:
providing a substrate including cell regions and peripheral regions;
selectively forming a gate conductive layer over the substrate in the peripheral regions;
forming a sealing layer over the substrate with the gate conductive layer formed thereon;
forming an insulation layer over the sealing layer to cover the substrate with the gate conductive layer formed on the substrate;
planarizing the insulation layer to expose the sealing layer formed over the gate conductive layer; and
forming a plurality of plugs in the cell regions, the plurality of the plugs penetrating the insulation layer and the sealing layer.
2. The method of claim 1 , further comprising:
forming a plurality of buried gates in the cell regions before the selective forming of the gate conductive layer or forming a plurality of buried gates in the cell regions after the selective forming of the gate conductive layer.
3. The method of claim 2 , wherein the forming of the plurality of the buried gates in the cell regions before the selective forming of the gate conductive layer includes:
forming a plurality of trenches by selectively etching the substrate in the cell regions;
forming a cell gate insulation layer over the plurality of the trenches;
forming cell gate electrodes over the cell gate insulation layer, each cell gate electrode filling a portion of a respective trench; and
forming a protective layer over the cell gate electrodes, the protective layer filling a remaining portion of each of the trenches.
4. The method of claim 2 , wherein the forming of the plurality of the buried gates in the cell regions after the selective forming of the gate conductive layer includes:
forming a plurality of trenches by selectively etching the substrate in the cell regions;
forming a cell gate insulation layer over the plurality of the trenches;
forming cell gate electrodes over the cell gate insulation layer, each cell gate electrode filling a portion of a respective trench; and
forming a sealing layer over the substrate including the gate conductive layer to fill a remaining portion of each of the trenches.
5. The method of claim 1 , wherein the selective forming of the gate conductive layer over the substrate in the peripheral regions includes:
forming the gate conductive layer over the substrate; and
etching the gate conductive layer by using a cell open mask.
6. The method of claim 1 , wherein the insulation layer is planarized through a chemical mechanical polishing (CMP) process.
7. The method of claim 1 , wherein the forming of the plurality of the plugs includes:
forming a plurality of contact holes exposing a surface of the substrate by selectively etching the insulation layer and the sealing layer;
depositing a plug conductive layer over the substrate to fill the contact holes; and
planarizing the plug conductive layer to expose an upper surface of the insulation layer.
8. The method of claim 7 , wherein the plug conductive layer is planarized through a chemical mechanical polishing process or a blanket etch process.
9. A method for fabricating a semiconductor device, comprising:
providing a substrate including cell regions and peripheral regions;
forming a gate conductive layer over the substrate;
etching the gate conductive layer by using a cell open mask;
forming a sealing layer over the substrate with the gate conductive layer formed thereon;
forming an insulation layer over the sealing layer to cover the substrate with the gate conductive layer formed on the substrate;
planarizing the insulation layer to expose the sealing layer formed over the gate conductive layer;
forming a plurality of plugs in the cell regions, the plurality of the plugs penetrating the insulation layer and the sealing layer;
selectively removing the sealing layer formed over the gate conductive layer; and
forming peripheral gates by patterning the gate conductive layer.
10. The method of claim 9 , further comprising:
forming a plurality of buried gates in the cell regions before the selective forming of the gate conductive layer or forming a plurality of buried gates in the cell regions after the selective forming of the gate conductive layer.
11. The method of claim 10 , wherein the forming of the plurality of the buried gates in the cell regions before the selective forming of the gate conductive layer includes:
forming a plurality of trenches by selectively etching the substrate in the cell regions;
forming a cell gate insulation layer over the plurality of the trenches;
forming cell gate electrodes over the cell gate insulation layer, each cell gate electrode filling a portion of a respective trench; and
forming a protective layer over the cell gate electrodes, the protective layer filling a remaining portion of each of the trenches.
12. The method of claim 10 , wherein the forming of the plurality of the buried gates in the cell regions after the selective forming of the gate conductive layer includes:
forming a plurality of trenches by selectively etching the substrate in the cell regions;
forming a cell gate insulation layer over the plurality of the trenches;
forming cell gate electrodes over the cell gate insulation layer, each cell gate electrode filling a portion of a respective trench; and
forming a sealing layer over the substrate including the gate conductive layer to fill a remaining portion of each of the trenches.
13. The method of claim 9 , wherein the etching of the gate conductive layer by using the cell open mask includes:
forming a photoresist layer pattern over the gate conductive layer by using the cell open mask, the photoresist pattern having the same linewidth as a predetermined linewidth of the peripheral regions; and
etching the gate conductive layer by using the photoresist layer pattern as an etch barrier.
14. The method of claim 9 , wherein the insulation layer is planarized through a chemical mechanical polishing (CMP) process.
15. The method of claim 14 , wherein the sealing layer is formed of a material having a selectivity with respect to the insulation layer.
16. The method of claim 15 , wherein the sealing layer includes a nitride layer, and the insulation layer includes an oxide layer.
17. The method of claim 9 , wherein the forming of the plurality of the plugs includes:
forming a plurality of contact holes exposing a surface of the substrate by selectively etching the insulation layer and the sealing layer;
depositing a plug conductive layer over the substrate to fill the contact holes; and
planarizing the plug conductive layer to expose an upper surface of the insulation layer.
18. The method of claim 17 , wherein the plug conductive layer is planarized through a chemical mechanical polishing process or a blanket etch process.
19. The method of claim 18 , wherein the plug conductive layer is formed of a material having a selectivity with respect to the sealing layer.
20. The method of claim 19 , wherein the sealing layer includes a nitride layer, and the plug conductive layer includes a single layer of a silicon layer or a metal layer, or a stacked layer where a silicon layer and a metal layer are stacked.
21. The method of claim 9 , wherein the sealing layer is selectively removed through a wet etch process.
22. The method of claim 21 , wherein the gate conductive layer is formed of a material having a selectivity with respect to the sealing layer.
23. The method of claim 22 , wherein the sealing layer includes a nitride layer, and the gate conductive layer includes a polysilicon layer.