IP Library Granted Patent US 8,334,598
Granted Patent B2
US 8,334,598 · App. 12/868,375 · Granted Dec 18, 2012

Power semiconductor device and manufacturing method therefor

Assignees: Mitsubishi Electric Corporation; Senju Metal Industry Co., Ltd.
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Quick Facts
Patent No.
US 8,334,598
App. No.
12/868,375
Granted
Dec 18, 2012
Kind
B2
Abstract

A power semiconductor device includes a substrate, an element circuit pattern formed on the substrate and made of Cu covered with an electroless Ni—P plating layer, and a power semiconductor element bonded to the element circuit pattern by a solder, wherein the solder is an alloy of Sn, Sb, and Cu, and the weight percent of Cu is in the range of 0.5 to 1%, inclusive.

Claims (24)

1. A power semiconductor device comprising:

a substrate;

an element circuit pattern formed on said substrate and made of Cu covered with an electroless Ni—P plating layer; and

a power semiconductor element bonded to said element circuit pattern by a solder;

wherein said solder is an alloy of Sn, Sb, and Cu, and the weight percent of Cu is in the range of 0.5 to 1%, inclusive.

2. The power semiconductor device according to claim 1 , wherein the weight percent of Sn in said alloy is in the range of 91 to 93%, inclusive, and the weight percent of Sb in said alloy is in the range of 6.5 to 8%, inclusive.

3. The power semiconductor device according to claim 2 , further comprising:

a terminal circuit pattern formed on said substrate; and

a terminal bonded to said terminal circuit pattern by a terminal solder;

wherein said terminal solder is an Sn—Ag-based or Sn—Ag—Cu-based unleaded solder having a liquidus temperature in the range of 215° to 220° C., inclusive; and

wherein said solder has a solidus temperature in the range of 235° to 238° C., inclusive.

4. The power semiconductor device according to claim 1 , wherein said Ni—P plating layer has a thickness in the range of 2 to 3 μm, inclusive.

5. A power semiconductor device comprising:

a substrate;

a circuit pattern which is an unplated Cu pattern formed on said substrate;

a power semiconductor element bonded to said circuit pattern by a solder made of an alloy of Sn, Sb, and Cu;

a terminal circuit pattern formed on said substrate;

a terminal bonded to said terminal circuit pattern by a terminal solder made of an Sn—Ag-based or Sn—Ag—Cu-based unleaded solder;

wherein the weight percent of Cu in said solder is in the range of 0.5 to 1%, inclusive, and said solder has a solidus temperature in the range of 235° to 238° C., inclusive; and

wherein said terminal solder has a liquidus temperature in the range of 215° to 220° C., inclusive.

6. The power semiconductor device according to claim 5 , further comprising:

a bottom surface pattern formed on the surface of said substrate opposite that on which said circuit pattern is formed; and

a heat sink bonded to said bottom surface pattern by a solder having the same composition as said solder;

wherein said heat sink is Cu and is not plated.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Aug 25, 2010
From: NISHIBORI, HIROSHI; YOSHIHARA, KUNIHIRO; UESHIMA, MINORU
To: MITSUBISHI ELECTRIC CORPORATION; SENJU METAL INDUSTRY CO., LTD.
Reel/Frame 024886/0891 →
Priority Claims (1)
JP 2009-238518 · Oct 15, 2009 · national
Continuity (1)
Related Publication 20110089568A1 · Apr 21, 2011