IP Library › Granted Patent US 8,334,719
Granted Patent B2
US 8,334,719 · App. 12/943,570 · Granted Dec 18, 2012

Semiconductor device having function of thyristor

Assignee: Semiconductor Energy Laboratory Co., Ltd.
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Quick Facts
Patent No.
US 8,334,719
App. No.
12/943,570
Granted
Dec 18, 2012
Kind
B2
Abstract

An object is to provide a semiconductor device that can realize a function of a thyristor without complication of the process. A semiconductor device including a memory circuit that stores a predetermined potential by reset operation and initialization operation is provided with a circuit that rewrite data in the memory circuit in accordance with supply of a trigger signal. The semiconductor device has a structure in which a current flowing through the semiconductor device is supplied to a load by rewriting data in the memory circuit, and thus can function as a thyristor.

Claims (31)

1. A semiconductor device comprising:

first to ninth insulated gate transistors;

a capacitor;

a buffer circuit;

a first wiring to which a first high power supply potential is supplied;

a second wiring to which a second high power supply potential is supplied;

a third wiring to which a first low power supply potential is supplied; and

a fourth wiring to which a second low power supply potential is supplied,

wherein a gate of the first insulated gate transistor is electrically connected to an input terminal, a first terminal of the first insulated gate transistor is electrically connected to the third wiring, and a second terminal of the first insulated gate transistor is electrically connected to a first terminal of the second insulated gate transistor,

wherein a gate of the second insulated gate transistor is electrically connected to a first terminal of the seventh insulated gate transistor and a first terminal of the eighth insulated gate transistor; and a second terminal of the second insulated gate transistor is electrically connected to a first terminal of the third insulated gate transistor, a first terminal of the fourth insulated gate transistor, and a gate of the sixth insulated gate transistor,

wherein a gate of the third insulated gate transistor is electrically connected to the first wiring, and a second terminal of the third insulated gate transistor is electrically connected to the second wiring,

wherein a gate of the fourth insulated gate transistor is electrically connected to a first terminal of the fifth insulated gate transistor, a first terminal of the sixth insulated gate transistor, a first electrode of the capacitor, a gate of the eighth insulated gate transistor, and a gate of the ninth insulated gate transistor through the buffer circuit; and a second terminal of the fourth insulated gate transistor is electrically connected to the third wiring,

wherein a gate of the fifth insulated gate transistor is electrically connected to the first wiring, and a second terminal of the fifth insulated gate transistor is electrically connected to the second wiring,

wherein a second terminal of the sixth insulated gate transistor is electrically connected to the third wiring,

wherein a gate of the seventh insulated gate transistor is electrically connected to the first wiring, and a second terminal of the seventh insulated gate transistor is electrically connected to the second wiring,

wherein a second terminal of the eighth insulated gate transistor is electrically connected to the third wiring,

wherein a first terminal of the ninth insulated gate transistor is electrically connected to an output terminal, and a second terminal of the ninth insulated gate transistor is electrically connected to the fourth wiring,

wherein a second electrode of the capacitor is electrically connected to the third wiring,

wherein the first to ninth insulated gate transistors each have a semiconductor layer formed using an oxide semiconductor, and

wherein a potential of a node at which the gate of the fourth insulated gate transistor, the first terminal of the fifth insulated gate transistor, the first terminal of the sixth insulated gate transistor, the first electrode of the capacitor, and the gate of the eighth insulated gate transistor are electrically connected is supplied to the gate of the ninth insulated gate transistor through the buffer circuit.

2. The semiconductor device according to claim 1 , further comprising a resistor,

wherein a first terminal of the resistor is electrically connected to the gate of the first insulated gate transistor, and a second terminal of the resistor is electrically connected to the third wiring.

3. The semiconductor device according to claim 1 , wherein a concentration of hydrogen in the oxide semiconductor detected by secondary ion mass spectrometry is 1×10 16 /cm 3 or less.

4. The semiconductor device according to claim 1 , wherein a carrier concentration of the oxide semiconductor is less than 1×10 14 /cm 3 .

5. The semiconductor device according to claim 1 , wherein the first high power supply potential and the second high power supply potential are the same potential.

6. The semiconductor device according to claim 1 ,

wherein the buffer circuit includes tenth to thirteenth insulated gate transistors,

wherein a gate of the tenth insulated gate transistor is electrically connected to the gate of the second insulated gate transistor, the first terminal of the seventh insulated gate transistor, and the first terminal of the eighth insulated gate transistor; a first terminal of the tenth insulated gate transistor is electrically connected to the second wiring; and a second terminal of the tenth insulated gate transistor is electrically connected to a first terminal of the eleventh insulated gate transistor and a gate of the thirteenth insulated gate transistor,

wherein a gate of the eleventh insulated gate transistor is electrically connected to the gate of the fourth insulated gate transistor, the first terminal of the fifth insulated gate transistor, the first terminal of the sixth insulated gate transistor, the first electrode of the capacitor, the gate of the eighth insulated gate transistor, and a gate of the twelfth insulated gate transistor; and a second terminal of the eleventh insulated gate transistor is electrically connected to the third wiring,

wherein a first terminal of the twelfth insulated gate transistor is electrically connected to the second wiring, and a second terminal of the twelfth insulated gate transistor is electrically connected to a first terminal of the thirteenth insulated gate transistor and the gate of the ninth insulated gate transistor, and

wherein a second terminal of the thirteenth insulated gate transistor is electrically connected to the third wiring.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Nov 10, 2010
From: KOYAMA, JUN; WATANABE, KAZUNORI
To: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.
Reel/Frame 025345/0378 →
Priority Claims (1)
JP 2009-259900 · Nov 13, 2009 · national
Continuity (1)
Related Publication 20110115545A1 · May 19, 2011