Forming a buried word line and connection pad for memory apparatus
A method for fabricating a semiconductor memory apparatus is provided to minimize failure of the semiconductor memory apparatus and to secure a processing margin. The method also provides for minimizing the deterioration of an operating speed and the operational stability, and minimizing the increase of resistance occurring as a result of a reduced processing margin when forming a gate pattern in a peripheral region of the semiconductor memory apparatus. The method includes forming a connection pad in a peripheral region while forming a buried word line in a cell region, and forming a gate pattern in the peripheral region while forming a bit line in the cell region.
1. A method for fabricating a semiconductor memory apparatus, the method comprising:
forming a connection pad in a peripheral region while forming a buried word line in a cell region; and
forming a gate pattern in the peripheral region while forming a bit line in the cell region.
2. The method of claim 1 , further comprising forming an isolation layer in the cell region and the peripheral region to define an active region.
3. The method of claim 2 , wherein the connection pad is formed in the isolation layer.
4. The method of claim 1 , wherein the gate pattern is formed over the connection pad.
5. The method of claim 1 , wherein the forming of the connection pad in the peripheral region while forming the buried word line in the cell region comprises:
forming a recess by etching the active region in the cell region and a trench by etching the isolation layer in the peripheral region, using a mask defining positions of the buried word line and the connection pad; and
filling the recess and the trench with a conductive material.
6. The method of claim 5 , further comprising:
selectively exposing the cell region and the peripheral region using a cell open/close mask, thereby forming a resultant structure; and
performing an etch-back process and a planarization process on the resultant structure.
7. The method of claim 5 , wherein the recess is formed with a depth greater than that of the trench.
8. The method of claim 1 , further comprising depositing an insulation layer in the cell region and the peripheral region after forming the buried word line and the connection pad.
9. The method of claim 8 , wherein the forming of the gate pattern in the peripheral region while forming the bit line in the cell region comprises:
etching the insulation layer using mask defining positions of the bit line and the gate pattern; and
filling a portion where the insulation layer is removed and the top surface of the active region is exposed with a conductive material.
10. The method of claim 1 , wherein, when forming the gate pattern in the peripheral region, a dummy gate pattern electrically disconnected with the connection pad is formed to have a length substantially the same as that of the gate pattern.
11. The method of claim 1 , further comprising forming contacts over the active region and the connection pad included in the peripheral region.
12. The method of claim 11 , wherein the contact formed over the connection pad has a length substantially the same as that of the contact formed over the active region.