IP Library Granted Patent US 8,338,304
Granted Patent B2
US 8,338,304 · App. 12/887,906 · Granted Dec 25, 2012

Methods to reduce the critical dimension of semiconductor devices and related semiconductor devices

Assignee: Micron Technology, Inc.
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Quick Facts
Patent No.
US 8,338,304
App. No.
12/887,906
Granted
Dec 25, 2012
Kind
B2
Abstract

A method of forming features on a target layer. The features have a critical dimension that is triple- or quadruple-reduced compared to the critical dimension of portions of a resist layer used as a mask. An intermediate layer is deposited over a target layer and the resist layer is formed over the intermediate layer. After patterning the resist layer, first spacers are formed on sidewalls of remaining portions of the resist layer, masking portions of the intermediate layer. Second spacers are formed on sidewalls of the portions of the intermediate layer. After removing the portions of the intermediate layer, the second spacers are used as a mask to foil the features on the target layer. A partially fabricated integrated circuit device is also disclosed.

Claims (18)

1. A method of forming features on a target layer, comprising:

forming openings in a resist layer having a first thickness located above an intermediate layer on a target layer;

forming a first set of spacers on sidewalls of the resist layer, the first set of spacers including a first material and having a second thickness at least one third the first thickness of the resist layer;

removing portions of the resist layer and the intermediate layer not masked by the first set of spacers;

exposing portions of the target layer except for portions masked by the first set of spacers;

removing the first set of spacers;

exposing remaining portions of the intermediate layer;

forming second spacers on sidewalls of the remaining portions of the intermediate layer such that a first portion of the second spacers are separated from first neighboring second spacers by a distance equal to a width of the second spacers, a second portion of the second spacers are separated from second neighboring second spacers by voids and the remaining portions of the intermediate layer, and a third portion of the second spacers are separated from third neighboring second spacers by the remaining portions of the intermediate layer on both sides of the third portion of the second spacers;

removing the remaining portions of the intermediate layer; and

forming features in exposed portions of the target layer, the features having a critical dimension about equal to the second thickness of the first set of spacers.

2. The method of claim 1 , wherein forming the second spacers on the sidewalls of the remaining portions of the intermediate layer comprises forming the second spacers from the first material.

3. The method of claim 1 , further comprising selecting the intermediate layer to be selectively etchable relative to the first material.

4. The method of claim 1 , further comprising forming an anti-reflective layer between the resist layer and the intermediate layer.

5. The method of claim 1 , wherein removing the portions of the resist layer and the intermediate layer not masked by the first set of spacers comprises creating an opening having a distance of about three times the thickness of the first spacers between some of the remaining portions of the intermediate layer.

6. The method of claim 1 , wherein removing the portions of the resist layer and the intermediate layer not masked by the first set of spacers comprises forming substantially vertical portions of the intermediate layer and the first set of spacers.

7. The method of claim 6 , wherein forming the substantially vertical portions of the intermediate layer and the first set of spacers comprises forming the substantially vertical portions of the intermediate layer and the first set of spacers having a thickness about equal to the second thickness of the first set of spacers.

8. The method of claim 1 , wherein forming the second spacers on the sidewalls of the remaining portions of the intermediate layer comprises forming the second spacers at a thickness about equal to the second thickness of the first set of spacers.

9. The method of claim 1 , wherein forming the openings in the resist layer located above the intermediate layer comprises forming the openings to have a third thickness of about three times the second thickness of the first set of spacers.

Assignments (7)
RELEASE OF SECURITY INTEREST Recorded Nov 12, 2019
From: JPMORGAN CHASE BANK, N.A., AS COLLATERAL AGENT
To: MICRON TECHNOLOGY, INC.; MICRON SEMICONDUCTOR PRODUCTS, INC.
Reel/Frame 051028/0001 →
RELEASE OF SECURITY INTEREST Recorded Oct 9, 2019
From: MORGAN STANLEY SENIOR FUNDING, INC., AS COLLATERAL AGENT
To: MICRON TECHNOLOGY, INC.
Reel/Frame 050937/0001 →
RELEASE OF SECURITY INTEREST Recorded Aug 23, 2018
From: U.S. BANK NATIONAL ASSOCIATION, AS COLLATERAL AGENT
To: MICRON TECHNOLOGY, INC.
Reel/Frame 047243/0001 →
SECURITY INTEREST Recorded Jul 13, 2018
From: MICRON TECHNOLOGY, INC.; MICRON SEMICONDUCTOR PRODUCTS, INC.
To: JPMORGAN CHASE BANK, N.A., AS COLLATERAL AGENT
Reel/Frame 047540/0001 →
CORRECTIVE ASSIGNMENT TO CORRECT THE REPLACE ERRONEOUSLY FILED PATENT #7358718 WITH THE CORRECT PATENT #7358178 PREVIOUSLY RECORDED ON REEL 038669 FRAME 0001. ASSIGNOR(S) HEREBY CONFIRMS THE SECURITY INTEREST. Recorded Jun 8, 2017
From: MICRON TECHNOLOGY, INC.
To: U.S. BANK NATIONAL ASSOCIATION, AS COLLATERAL AGENT
Reel/Frame 043079/0001 →
PATENT SECURITY AGREEMENT Recorded Jun 2, 2016
From: MICRON TECHNOLOGY, INC.
To: MORGAN STANLEY SENIOR FUNDING, INC., AS COLLATERAL AGENT
Reel/Frame 038954/0001 →
SECURITY INTEREST Recorded May 12, 2016
From: MICRON TECHNOLOGY, INC.
To: U.S. BANK NATIONAL ASSOCIATION, AS COLLATERAL AGENT
Reel/Frame 038669/0001 →
Continuity (2)
Division 11606613 · Nov 29, 2006
Related Publication 20110006402A1 · Jan 13, 2011