IP Library Granted Patent US 8,338,861
Granted Patent B2
US 8,338,861 · App. 12/008,190 · Granted Dec 25, 2012

III-nitride semiconductor device with stepped gate trench and process for its manufacture

Assignee: International Rectifier Corporation
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Quick Facts
Patent No.
US 8,338,861
App. No.
12/008,190
Granted
Dec 25, 2012
Kind
B2
Abstract

A III-nitride heterojunction power semiconductor device that includes a passivation body with a gate well having a top mouth that is wider than the bottom mouth thereof, and a method of fabrication for the same.

Claims (26)

1. A III-nitride semiconductor device, comprising:

a III-nitride heterojunction that includes a first III-nitride body having one band gap, and a second III-nitride body having another band gap disposed over said first III-nitride body to form a two dimensional electron gas;

a passivation body formed over said second III-nitride body,

said passivation body including a gate well having a first mouth at said second III-nitride body and a second mouth wider than said first mouth at the top of said passivation body,

said second mouth defined by sidewalls within said passivation body,

said passivation body comprising a first ledge and a second ledge to define said first mouth, wherein said first ledge is wider than said second ledge; and

a gate arrangement disposed at least partially within said gate well, said gate arrangement including a gate insulation disposed at said first mouth of said well and a gate electrode over said gate insulation, said gate arrangement filling said second mouth of said gate well.

2. The device of claim 1 , further comprising a drain electrode and a source electrode on respective sides of said gate arrangement, wherein said first ledge is at a sidewall of said gate well closer to said drain electrode than said source electrode.

3. The device of claim 1 , wherein said ledges are comprised of silicon nitride.

4. The device of claim 1 , wherein said passivation body includes a first insulation body over said second III-nitride body and a second insulation body over said first insulation body.

5. The device of claim 4 , wherein said first insulation body is comprised of silicon nitride, and said second insulation body is comprised of a nitride dielectric.

6. The device of claim 5 , wherein said second insulation is comprised of AlN.

7. The device of claim 5 , wherein said second insulation is comprised of TiN.

8. The device of claim 1 , wherein said first III-nitride body is comprised of GaN and said second III-nitride body is comprised of AlGaN.

9. A method of fabricating a III-nitride device, comprising:

forming a first insulation body over a III-nitride heterojunction that includes a first III-nitride body having one band gap, and a second III-nitride body having another band gap disposed over said first III-nitride body to form a two dimensional electron gas;

forming a second insulation body over said first insulation body;

forming a trench through said first and second insulation bodies, said trench including a first mouth at said second III-nitride body and a second mouth at the top of said second insulation body; and

etching sidewalls of said trench to remove portions of said second insulation body thereby opening said second mouth wider than said first mouth and forming a first and a second ledge from said first insulation body to define said first mouth, said first ledge wider than said second ledge.

10. The method of claim 9 , wherein said first insulation body is comprised of silicon nitride, and said second insulation body is comprised of a nitride dielectric.

11. The method of claim 10 , wherein said second insulation is comprised of AlN.

12. The method of claim 10 , wherein said second insulation is comprised of TiN.

13. The method of claim 9 , wherein said first III-nitride body is comprised of GaN and said second III-nitride body is comprised of AlGaN.

14. The method of claim 9 , further comprising forming a gate arrangement in said trench.

15. The method of claim 14 , wherein said gate arrangement includes a gate dielectric body over said second III-nitride body and a gate electrode over said gate dielectric.

16. The method of claim 9 , further comprising forming a drain electrode and a source electrode on respective sides of said gate arrangement, wherein said first ledge is at a side of said gate arrangement closer to said drain electrode than said source electrode.

Assignments (2)
MERGER AND CHANGE OF NAME Recorded Apr 4, 2016
From: INTERNATIONAL RECTIFIER CORPORATION; INFINEON TECHNOLOGIES AMERICAS CORP.
To: INFINEON TECHNOLOGIES AMERICAS CORP.
Reel/Frame 038185/0885 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jun 9, 2008
From: BRIERE, MICHAEL A.; BRIDGER, PAUL; CAO, JIANJUN
To: INTERNATIONAL RECTIFIER CORPORATION
Reel/Frame 021069/0416 →
Continuity (2)
Provisional Application 60884272 · Jan 10, 2007
Related Publication 20090189187A1 · Jul 30, 2009