Semiconductor device with (110)-oriented silicon
A vertical semiconductor device includes a bottom metal layer and a first P-type semiconductor layer overlying the bottom metal layer. The first P-type semiconductor layer is characterized by a surface crystal orientation of (110) and a first conductivity. The first P-type semiconductor layer is heavily doped. The vertical semiconductor device also includes a second P-type semiconductor layer overlying the first P-type semiconductor layer. The second semiconductor layer has a surface crystal orientation of (110) and is characterized by a lower conductivity than the first conductivity. The vertical semiconductor device also has a top metal layer overlying the second P-type semiconductor layer. A current conduction from the top metal layer to the bottom metal layer and through the second p-type semiconductor layer is characterized by a hole mobility along a <110> crystalline orientation and on (110) crystalline plane.
1. A vertical semiconductor device, comprising:
a bottom metal layer;
a first P-type semiconductor layer overlying the bottom metal layer, the first P-type semiconductor layer being characterized by a surface crystal orientation of (110) and a first conductivity, the first P-type semiconductor layer being heavily doped;
a second P-type semiconductor layer overlying the first P-type semiconductor layer, the second semiconductor layer having a surface crystal orientation of (110) and being characterized by a lower conductivity than the first conductivity; and
a top metal layer overlying the second P-type semiconductor layer,
wherein a current conduction from the top metal layer to the bottom metal layer and through the second p-type semiconductor layer is characterized by a hole mobility along a <110> crystalline orientation and on (110) crystalline plane.
2. The vertical semiconductor device of claim 1 wherein the first P-type semiconductor layer is characterized by a doping concentration of 1×10 17 cm −3 or higher.
3. The vertical semiconductor device of claim 1 wherein the first P-type semiconductor layer is characterized by a doping concentration higher than 6×10 19 cm −3 .
4. The vertical semiconductor device of claim 1 wherein a thickness of the first P-type semiconductor layer is between approximately 0.5 μm to approximately 3 μm.
5. The vertical semiconductor device of claim 1 wherein each of the first and second P-type semiconductor layers is an epitaxial layer.
6. The vertical semiconductor device of claim 1 wherein the bottom metal layer has sufficient thickness for supporting the vertical semiconductor device.
7. The vertical semiconductor device of claim 1 wherein the vertical semiconductor device comprises a trench gate P-channel MOSFET, the trench gate MOSFET further comprising:
a trench extending into the second P-type semiconductor region; a gate dielectric layer lining sidewalls and bottom of the trench;
a gate electrode over the gate dielectric in the trench;
P-type source regions flanking each side of the gate electrode in the trench;
a P-type drift region;
an N-type body region extending over the drift region; and
a P-type drain region including at least a portion of the heavily doped first P-type semiconductor layer.
8. The vertical semiconductor device of claim 1 wherein the vertical semiconductor device comprises a P-channel shielded gate trench MOSFET, the shielded gate trench MOSFET further comprising:
a trench extending into the second P-type semiconductor layer;
a shield dielectric lining sidewalls and a bottom surface of the trench;
a shield electrode in a lower portion of the trench, the shield electrode being insulated from the second semiconductor layer by the shield dielectric;
an inter-electrode dielectric overlying the shield electrode;
a gate dielectric lining upper portions of trench sidewalls; and
a gate electrode in an upper portion of the trench over the inter-electrode dielectric, the gate electrode being insulated from the second P-type semiconductor layer by the gate dielectric.
9. The vertical semiconductor device of claim 8 wherein the second P-type semiconductor layer comprises:
a P-type drift region;
an N-type body region extending over the drift region; and
P-type source regions in the body region adjacent to the trench.
10. A vertical trench gate MOSFET device formed in a (110) substrate, comprising:
a bottom metal layer;
a first P-type semiconductor layer overlying the bottom metal layer, the first P-type semiconductor layer being characterized by a surface crystal orientation of (110) and a first conductivity, the first P-type semiconductor layer being heavily doped;
a second P-type semiconductor layer having a surface crystal orientation of (110) and overlying the first P-type semiconductor layer, the second semiconductor layer—being characterized by a lower conductivity than the first conductivity;
an N-type body region in the second P-type semiconductor layer; and
a trench extending through the body region and into a bottom portion of the second P-type semiconductor layer underlying the body region;
a gate dielectric layer lining sidewalls and bottom of the trench;
a gate electrode over the gate dielectric in the trench;
P-type source regions flanking each side of the gate electrode in the trench; and
a top metal layer overlying the second P-type semiconductor layer, the top metal layer being coupled to the source regions and the body region,
wherein a current conduction from the top metal layer to the bottom metal layer and through the second P-type semiconductor layer is characterized by a hole mobility along a <110> crystalline orientation.
11. The vertical semiconductor device of claim 10 wherein the first P-type semiconductor layer is characterized by a doping concentration of 1×10 17 cm −3 or higher.
12. The vertical semiconductor device of claim 10 wherein the first P-type semiconductor layer is characterized by a doping concentration higher than 6×10 19 cm −3 .
13. The vertical semiconductor device of claim 10 wherein a thickness of the first P-type semiconductor layer is between approximately 0.5 μm to approximately 3 μm.
14. The vertical semiconductor device of claim 10 wherein each of the first and second P-type semiconductor layers is an epitaxial layer.
15. The vertical semiconductor device of claim 10 wherein the bottom metal layer has sufficient thickness for supporting the vertical semiconductor device.
16. A vertical shielded gate trench MOSFET device formed in a (110) substrate, comprising:
a bottom metal layer;
a first P-type semiconductor layer overlying the bottom metal layer, the first P-type semiconductor layer being characterized by a surface crystal orientation of (110) and a first conductivity, the first P-type semiconductor layer being heavily doped;
a second P-type semiconductor layer having a surface crystal orientation of (110) and overlying the first P-type semiconductor layer, the second P-type semiconductor layer being characterized by a lower conductivity than the first conductivity;
an N-type body region in the second P-type semiconductor layer;
a trench extending through the body region and into a bottom portion of the second P-type semiconductor layer underlying the body region;
a shield dielectric lining sidewalls and a bottom surface of the trench, the shield dielectric including a first shield oxide layer;
a shield electrode in a lower portion of the trench, the shield electrode being insulated from the semiconductor region by the shield dielectric;
an inter-electrode dielectric overlying the shield electrode; a gate dielectric lining upper portions of trench sidewalls;
a gate electrode in an upper portion of the trench over the inter-electrode dielectric, the gate electrode being insulated from the semiconductor region by the gate dielectric;
P-type source regions flanking each side of the gate electrode in the trench; and
a top metal layer overlying the second P-type semiconductor layer, the top metal layer being coupled to the source regions and the body region; wherein a current conduction from the top metal layer to the bottom metal layer and through the second P-type semiconductor layer is characterized by a hole mobility along a <110> crystalline orientation and in a (110) crystalline plane.
17. The vertical semiconductor device of claim 16 wherein the first P-type semiconductor layer is characterized by a doping concentration of 1×10 17 cm −3 or higher.
18. The vertical semiconductor device of claim 16 wherein the first P-type semiconductor layer is characterized by a doping concentration higher than 6×10 19 cm −3 .
19. The vertical semiconductor device of claim 16 wherein a thickness of the first P-type semiconductor layer is between approximately 0.5 μm to approximately 3 μm.
20. The vertical semiconductor device of claim 16 wherein each of the first and second P-type semiconductor layers is an epitaxial layer.
21. The vertical semiconductor device of claim 16 wherein the bottom metal layer has sufficient thickness for supporting the vertical semiconductor device.